linux-imx

/*

 * Copyright (C) 2016 Broadcom

 *  Author: Jayachandran C <jchandra@broadcom.com>

 * Copyright (C) 2016 Semihalf

 *  Author: Tomasz Nowicki <tn@semihalf.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License, version 2, as

 * published by the Free Software Foundation (the "GPL").

 *

 * This program is distributed in the hope that it will be useful, but

 * WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * General Public License version 2 (GPLv2) for more details.

 *

 * You should have received a copy of the GNU General Public License

 * version 2 (GPLv2) along with this source code.

 */

​

#define pr_fmt(fmt) "ACPI: " fmt

​

#include <linux/kernel.h>

#include <linux/pci.h>

#include <linux/pci-acpi.h>

#include <linux/pci-ecam.h>

​

/* Structure to hold entries from the MCFG table */

struct mcfg_entry {

    struct list_head    list;

    phys_addr_t     addr;

    u16         segment;

    u8          bus_start;

    u8          bus_end;

};

​

#ifdef CONFIG_PCI_QUIRKS

struct mcfg_fixup {

    char oem_id[ACPI_OEM_ID_SIZE + 1];

    char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];

    u32 oem_revision;

    u16 segment;

    struct resource bus_range;

    struct pci_ecam_ops *ops;

    struct resource cfgres;

};

​

#define MCFG_BUS_RANGE(start, end)  DEFINE_RES_NAMED((start),   \

                        ((end) - (start) + 1),  \

                        NULL, IORESOURCE_BUS)

#define MCFG_BUS_ANY            MCFG_BUS_RANGE(0x0, 0xff)

​

static struct mcfg_fixup mcfg_quirks[] = {

/*  { OEM_ID, OEM_TABLE_ID, REV, SEGMENT, BUS_RANGE, ops, cfgres }, */

​

#define QCOM_ECAM32(seg) \

    { "QCOM  ", "QDF2432 ", 1, seg, MCFG_BUS_ANY, &pci_32b_ops }

​

    QCOM_ECAM32(0),

    QCOM_ECAM32(1),

    QCOM_ECAM32(2),

    QCOM_ECAM32(3),

    QCOM_ECAM32(4),

    QCOM_ECAM32(5),

    QCOM_ECAM32(6),

    QCOM_ECAM32(7),

​

#define HISI_QUAD_DOM(table_id, seg, ops) \

    { "HISI  ", table_id, 0, (seg) + 0, MCFG_BUS_ANY, ops }, \

    { "HISI  ", table_id, 0, (seg) + 1, MCFG_BUS_ANY, ops }, \

    { "HISI  ", table_id, 0, (seg) + 2, MCFG_BUS_ANY, ops }, \

    { "HISI  ", table_id, 0, (seg) + 3, MCFG_BUS_ANY, ops }

​

    HISI_QUAD_DOM("HIP05   ",  0, &hisi_pcie_ops),

    HISI_QUAD_DOM("HIP06   ",  0, &hisi_pcie_ops),

    HISI_QUAD_DOM("HIP07   ",  0, &hisi_pcie_ops),

    HISI_QUAD_DOM("HIP07   ",  4, &hisi_pcie_ops),

    HISI_QUAD_DOM("HIP07   ",  8, &hisi_pcie_ops),

    HISI_QUAD_DOM("HIP07   ", 12, &hisi_pcie_ops),

​

#define THUNDER_PEM_RES(addr, node) \

    DEFINE_RES_MEM((addr) + ((u64) (node) << 44), 0x39 * SZ_16M)

​

#define THUNDER_PEM_QUIRK(rev, node) \

    { "CAVIUM", "THUNDERX", rev, 4 + (10 * (node)), MCFG_BUS_ANY,       \

      &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88001f000000UL, node) },  \

    { "CAVIUM", "THUNDERX", rev, 5 + (10 * (node)), MCFG_BUS_ANY,       \

      &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x884057000000UL, node) },  \

    { "CAVIUM", "THUNDERX", rev, 6 + (10 * (node)), MCFG_BUS_ANY,       \

      &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88808f000000UL, node) },  \

    { "CAVIUM", "THUNDERX", rev, 7 + (10 * (node)), MCFG_BUS_ANY,       \

      &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89001f000000UL, node) },  \

    { "CAVIUM", "THUNDERX", rev, 8 + (10 * (node)), MCFG_BUS_ANY,       \