linux-imx

/*

 * Broadcom SATA3 AHCI Controller Driver

 *

 * Copyright © 2009-2015 Broadcom Corporation

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2, or (at your option)

 * any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

​

#include <linux/ahci_platform.h>

#include <linux/compiler.h>

#include <linux/device.h>

#include <linux/init.h>

#include <linux/interrupt.h>

#include <linux/io.h>

#include <linux/kernel.h>

#include <linux/libata.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/platform_device.h>

#include <linux/reset.h>

#include <linux/string.h>

​

#include "ahci.h"

​

#define DRV_NAME                    "brcm-ahci"

​

#define SATA_TOP_CTRL_VERSION               0x0

#define SATA_TOP_CTRL_BUS_CTRL              0x4

 #define MMIO_ENDIAN_SHIFT              0 /* CPU->AHCI */

 #define DMADESC_ENDIAN_SHIFT               2 /* AHCI->DDR */

 #define DMADATA_ENDIAN_SHIFT               4 /* AHCI->DDR */

 #define PIODATA_ENDIAN_SHIFT               6

  #define ENDIAN_SWAP_NONE              0

  #define ENDIAN_SWAP_FULL              2

#define SATA_TOP_CTRL_TP_CTRL               0x8

#define SATA_TOP_CTRL_PHY_CTRL              0xc

 #define SATA_TOP_CTRL_PHY_CTRL_1           0x0

  #define SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE   BIT(14)

 #define SATA_TOP_CTRL_PHY_CTRL_2           0x4

  #define SATA_TOP_CTRL_2_SW_RST_MDIOREG        BIT(0)

  #define SATA_TOP_CTRL_2_SW_RST_OOB            BIT(1)

  #define SATA_TOP_CTRL_2_SW_RST_RX         BIT(2)

  #define SATA_TOP_CTRL_2_SW_RST_TX         BIT(3)

  #define SATA_TOP_CTRL_2_PHY_GLOBAL_RESET      BIT(14)

 #define SATA_TOP_CTRL_PHY_OFFS             0x8

 #define SATA_TOP_MAX_PHYS              2

​

#define SATA_FIRST_PORT_CTRL                0x700

#define SATA_NEXT_PORT_CTRL_OFFSET          0x80

#define SATA_PORT_PCTRL6(reg_base)          (reg_base + 0x18)

​

/* On big-endian MIPS, buses are reversed to big endian, so switch them back */

#if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)

#define DATA_ENDIAN          2 /* AHCI->DDR inbound accesses */

#define MMIO_ENDIAN          2 /* CPU->AHCI outbound accesses */