linux-imx

/*

 * AppliedMicro X-Gene SoC SATA Host Controller Driver

 *

 * Copyright (c) 2014, Applied Micro Circuits Corporation

 * Author: Loc Ho <lho@apm.com>

 *         Tuan Phan <tphan@apm.com>

 *         Suman Tripathi <stripathi@apm.com>

 *

 * This program is free software; you can redistribute  it and/or modify it

 * under  the terms of  the GNU General  Public License as published by the

 * Free Software Foundation;  either version 2 of the  License, or (at your

 * option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

 *

 * NOTE: PM support is not currently available.

 *

 */

#include <linux/acpi.h>

#include <linux/module.h>

#include <linux/platform_device.h>

#include <linux/ahci_platform.h>

#include <linux/of_address.h>

#include <linux/of_device.h>

#include <linux/of_irq.h>

#include <linux/phy/phy.h>

#include "ahci.h"

​

#define DRV_NAME "xgene-ahci"

​

/* Max # of disk per a controller */

#define MAX_AHCI_CHN_PERCTR     2

​

/* MUX CSR */

#define SATA_ENET_CONFIG_REG        0x00000000

#define  CFG_SATA_ENET_SELECT_MASK  0x00000001

​

/* SATA core host controller CSR */

#define SLVRDERRATTRIBUTES      0x00000000

#define SLVWRERRATTRIBUTES      0x00000004

#define MSTRDERRATTRIBUTES      0x00000008

#define MSTWRERRATTRIBUTES      0x0000000c

#define BUSCTLREG           0x00000014

#define IOFMSTRWAUX         0x00000018

#define INTSTATUSMASK           0x0000002c

#define ERRINTSTATUS            0x00000030

#define ERRINTSTATUSMASK        0x00000034

​

/* SATA host AHCI CSR */

#define PORTCFG             0x000000a4

#define  PORTADDR_SET(dst, src) \

        (((dst) & ~0x0000003f) | (((u32)(src)) & 0x0000003f))

#define PORTPHY1CFG     0x000000a8

#define PORTPHY1CFG_FRCPHYRDY_SET(dst, src) \

        (((dst) & ~0x00100000) | (((u32)(src) << 0x14) & 0x00100000))

#define PORTPHY2CFG         0x000000ac

#define PORTPHY3CFG         0x000000b0

#define PORTPHY4CFG         0x000000b4

#define PORTPHY5CFG         0x000000b8

#define SCTL0               0x0000012C

#define PORTPHY5CFG_RTCHG_SET(dst, src) \

        (((dst) & ~0xfff00000) | (((u32)(src) << 0x14) & 0xfff00000))

#define PORTAXICFG_EN_CONTEXT_SET(dst, src) \

        (((dst) & ~0x01000000) | (((u32)(src) << 0x18) & 0x01000000))

#define PORTAXICFG          0x000000bc

#define PORTAXICFG_OUTTRANS_SET(dst, src) \

        (((dst) & ~0x00f00000) | (((u32)(src) << 0x14) & 0x00f00000))

#define PORTRANSCFG         0x000000c8

#define PORTRANSCFG_RXWM_SET(dst, src)      \

        (((dst) & ~0x0000007f) | (((u32)(src)) & 0x0000007f))

​

/* SATA host controller AXI CSR */

#define INT_SLV_TMOMASK         0x00000010

​

/* SATA diagnostic CSR */

#define CFG_MEM_RAM_SHUTDOWN        0x00000070

#define BLOCK_MEM_RDY           0x00000074

​

/* Max retry for link down */

#define MAX_LINK_DOWN_RETRY 3

​

enum xgene_ahci_version {

    XGENE_AHCI_V1 = 1,

    XGENE_AHCI_V2,

};

​