linux-imx

/*

 * Faraday Technology FTIDE010 driver

 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>

 *

 * Includes portions of the SL2312/SL3516/Gemini PATA driver

 * Copyright (C) 2003 StorLine, Inc <jason@storlink.com.tw>

 * Copyright (C) 2009 Janos Laube <janos.dev@gmail.com>

 * Copyright (C) 2010 Frederic Pecourt <opengemini@free.fr>

 * Copyright (C) 2011 Tobias Waldvogel <tobias.waldvogel@gmail.com>

 */

​

#include <linux/platform_device.h>

#include <linux/module.h>

#include <linux/libata.h>

#include <linux/bitops.h>

#include <linux/of_address.h>

#include <linux/of_device.h>

#include <linux/clk.h>

#include "sata_gemini.h"

​

#define DRV_NAME "pata_ftide010"

​

/**

 * struct ftide010 - state container for the Faraday FTIDE010

 * @dev: pointer back to the device representing this controller

 * @base: remapped I/O space address

 * @pclk: peripheral clock for the IDE block

 * @host: pointer to the ATA host for this device

 * @master_cbl: master cable type

 * @slave_cbl: slave cable type

 * @sg: Gemini SATA bridge pointer, if running on the Gemini

 * @master_to_sata0: Gemini SATA bridge: the ATA master is connected

 * to the SATA0 bridge

 * @slave_to_sata0: Gemini SATA bridge: the ATA slave is connected

 * to the SATA0 bridge

 * @master_to_sata1: Gemini SATA bridge: the ATA master is connected

 * to the SATA1 bridge

 * @slave_to_sata1: Gemini SATA bridge: the ATA slave is connected

 * to the SATA1 bridge

 */

struct ftide010 {

    struct device *dev;

    void __iomem *base;

    struct clk *pclk;

    struct ata_host *host;

    unsigned int master_cbl;

    unsigned int slave_cbl;

    /* Gemini-specific properties */

    struct sata_gemini *sg;

    bool master_to_sata0;

    bool slave_to_sata0;

    bool master_to_sata1;

    bool slave_to_sata1;

};

​

#define FTIDE010_DMA_REG    0x00

#define FTIDE010_DMA_STATUS 0x02

#define FTIDE010_IDE_BMDTPR 0x04

#define FTIDE010_IDE_DEVICE_ID  0x08

#define FTIDE010_PIO_TIMING 0x10

#define FTIDE010_MWDMA_TIMING   0x11

#define FTIDE010_UDMA_TIMING0   0x12 /* Master */

#define FTIDE010_UDMA_TIMING1   0x13 /* Slave */

#define FTIDE010_CLK_MOD    0x14

/* These registers are mapped directly to the IDE registers */

#define FTIDE010_CMD_DATA   0x20

#define FTIDE010_ERROR_FEATURES 0x21

#define FTIDE010_NSECT      0x22

#define FTIDE010_LBAL       0x23

#define FTIDE010_LBAM       0x24

#define FTIDE010_LBAH       0x25

#define FTIDE010_DEVICE     0x26

#define FTIDE010_STATUS_COMMAND 0x27

#define FTIDE010_ALTSTAT_CTRL   0x36

​

/* Set this bit for UDMA mode 5 and 6 */

#define FTIDE010_UDMA_TIMING_MODE_56    BIT(7)

​

/* 0 = 50 MHz, 1 = 66 MHz */

#define FTIDE010_CLK_MOD_DEV0_CLK_SEL   BIT(0)

#define FTIDE010_CLK_MOD_DEV1_CLK_SEL   BIT(1)

/* Enable UDMA on a device */

#define FTIDE010_CLK_MOD_DEV0_UDMA_EN   BIT(4)

#define FTIDE010_CLK_MOD_DEV1_UDMA_EN   BIT(5)

​

static struct scsi_host_template pata_ftide010_sht = {

    ATA_BMDMA_SHT(DRV_NAME),

};

​

/*

 * Bus timings

 *