linux-imx

/*

 * Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.

 *

 * This driver is heavily based upon:

 *

 * linux/drivers/ide/pci/hpt366.c       Version 0.36    April 25, 2003

 *

 * Copyright (C) 1999-2003      Andre Hedrick <andre@linux-ide.org>

 * Portions Copyright (C) 2001          Sun Microsystems, Inc.

 * Portions Copyright (C) 2003      Red Hat Inc

 *

 *

 * TODO

 *  Look into engine reset on timeout errors. Should not be required.

 */

​

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

​

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/pci.h>

#include <linux/blkdev.h>

#include <linux/delay.h>

#include <scsi/scsi_host.h>

#include <linux/libata.h>

​

#define DRV_NAME    "pata_hpt366"

#define DRV_VERSION "0.6.11"

​

struct hpt_clock {

    u8  xfer_mode;

    u32 timing;

};

​

/* key for bus clock timings

 * bit

 * 0:3    data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.

 *        cycles = value + 1

 * 4:7    data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.

 *        cycles = value + 1

 * 8:11   cmd_high_time. Inactive time of DIOW_/DIOR_ during task file

 *        register access.

 * 12:15  cmd_low_time. Active time of DIOW_/DIOR_ during task file

 *        register access.

 * 16:18  udma_cycle_time. Clock cycles for UDMA xfer?

 * 19:21  pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.

 * 22:24  cmd_pre_high_time. Time to initialize 1st PIO cycle for task file

 *        register access.

 * 28     UDMA enable.

 * 29     DMA  enable.

 * 30     PIO_MST enable. If set, the chip is in bus master mode during

 *        PIO xfer.

 * 31     FIFO enable.

 */

​

static const struct hpt_clock hpt366_40[] = {

    {   XFER_UDMA_4,    0x900fd943  },

    {   XFER_UDMA_3,    0x900ad943  },

    {   XFER_UDMA_2,    0x900bd943  },

    {   XFER_UDMA_1,    0x9008d943  },

    {   XFER_UDMA_0,    0x9008d943  },

​

    {   XFER_MW_DMA_2,  0xa008d943  },

    {   XFER_MW_DMA_1,  0xa010d955  },

    {   XFER_MW_DMA_0,  0xa010d9fc  },

​

    {   XFER_PIO_4, 0xc008d963  },

    {   XFER_PIO_3, 0xc010d974  },

    {   XFER_PIO_2, 0xc010d997  },

    {   XFER_PIO_1, 0xc010d9c7  },

    {   XFER_PIO_0, 0xc018d9d9  },

    {   0,      0x0120d9d9  }

};

​

static const struct hpt_clock hpt366_33[] = {

    {   XFER_UDMA_4,    0x90c9a731  },

    {   XFER_UDMA_3,    0x90cfa731  },

    {   XFER_UDMA_2,    0x90caa731  },

    {   XFER_UDMA_1,    0x90cba731  },

    {   XFER_UDMA_0,    0x90c8a731  },

​

    {   XFER_MW_DMA_2,  0xa0c8a731  },

    {   XFER_MW_DMA_1,  0xa0c8a732  },  /* 0xa0c8a733 */

    {   XFER_MW_DMA_0,  0xa0c8a797  },

​

    {   XFER_PIO_4, 0xc0c8a731  },

    {   XFER_PIO_3, 0xc0c8a742  },

    {   XFER_PIO_2, 0xc0d0a753  },

    {   XFER_PIO_1, 0xc0d0a7a3  },  /* 0xc0d0a793 */

    {   XFER_PIO_0, 0xc0d0a7aa  },  /* 0xc0d0a7a7 */

    {   0,      0x0120a7a7  }

};