linux-imx

/*

 * Libata driver for the HighPoint 371N, 372N, and 302N UDMA66 ATA controllers.

 *

 * This driver is heavily based upon:

 *

 * linux/drivers/ide/pci/hpt366.c       Version 0.36    April 25, 2003

 *

 * Copyright (C) 1999-2003      Andre Hedrick <andre@linux-ide.org>

 * Portions Copyright (C) 2001          Sun Microsystems, Inc.

 * Portions Copyright (C) 2003      Red Hat Inc

 * Portions Copyright (C) 2005-2010 MontaVista Software, Inc.

 *

 *

 * TODO

 *  Work out best PLL policy

 */

​

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

​

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/pci.h>

#include <linux/blkdev.h>

#include <linux/delay.h>

#include <scsi/scsi_host.h>

#include <linux/libata.h>

​

#define DRV_NAME    "pata_hpt3x2n"

#define DRV_VERSION "0.3.15"

​

enum {

    HPT_PCI_FAST    =   (1 << 31),

    PCI66       =   (1 << 1),

    USE_DPLL    =   (1 << 0)

};

​

struct hpt_clock {

    u8  xfer_speed;

    u32 timing;

};

​

struct hpt_chip {

    const char *name;

    struct hpt_clock *clocks[3];

};

​

/* key for bus clock timings

 * bit

 * 0:3    data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.

 *        cycles = value + 1

 * 4:8    data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.

 *        cycles = value + 1

 * 9:12   cmd_high_time. Inactive time of DIOW_/DIOR_ during task file

 *        register access.

 * 13:17  cmd_low_time. Active time of DIOW_/DIOR_ during task file

 *        register access.

 * 18:20  udma_cycle_time. Clock cycles for UDMA xfer.

 * 21     CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock.

 * 22:24  pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.

 * 25:27  cmd_pre_high_time. Time to initialize 1st PIO cycle for task file

 *        register access.

 * 28     UDMA enable.

 * 29     DMA  enable.

 * 30     PIO_MST enable. If set, the chip is in bus master mode during

 *        PIO xfer.

 * 31     FIFO enable. Only for PIO.

 */

​

/* 66MHz DPLL clocks */

​

static struct hpt_clock hpt3x2n_clocks[] = {

    {   XFER_UDMA_7,    0x1c869c62  },

    {   XFER_UDMA_6,    0x1c869c62  },

    {   XFER_UDMA_5,    0x1c8a9c62  },

    {   XFER_UDMA_4,    0x1c8a9c62  },

    {   XFER_UDMA_3,    0x1c8e9c62  },

    {   XFER_UDMA_2,    0x1c929c62  },

    {   XFER_UDMA_1,    0x1c9a9c62  },

    {   XFER_UDMA_0,    0x1c829c62  },

​

    {   XFER_MW_DMA_2,  0x2c829c62  },

    {   XFER_MW_DMA_1,  0x2c829c66  },

    {   XFER_MW_DMA_0,  0x2c829d2e  },

​

    {   XFER_PIO_4, 0x0c829c62  },

    {   XFER_PIO_3, 0x0c829c84  },

    {   XFER_PIO_2, 0x0c829ca6  },

    {   XFER_PIO_1, 0x0d029d26  },

    {   XFER_PIO_0, 0x0d029d5e  },

};

​

/**