linux-imx

/*

 *    pata_ns87415.c - NS87415 (non PARISC) PATA

 *

 *  (C) 2005 Red Hat <alan@lxorguk.ukuu.org.uk>

 *

 *    This is a fairly generic MWDMA controller. It has some limitations

 *    as it requires timing reloads on PIO/DMA transitions but it is otherwise

 *    fairly well designed.

 *

 *    This driver assumes the firmware has left the chip in a valid ST506

 *    compliant state, either legacy IRQ 14/15 or native INTA shared. You

 *    may need to add platform code if your system fails to do this.

 *

 *    The same cell appears in the 87560 controller used by some PARISC

 *    systems. This has its own special mountain of errata.

 *

 *    TODO:

 *  Test PARISC SuperIO

 *  Get someone to test on SPARC

 *  Implement lazy pio/dma switching for better performance

 *  8bit shared timing.

 *  See if we need to kill the FIFO for ATAPI

 */

​

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/pci.h>

#include <linux/blkdev.h>

#include <linux/delay.h>

#include <linux/device.h>

#include <scsi/scsi_host.h>

#include <linux/libata.h>

#include <linux/ata.h>

​

#define DRV_NAME    "pata_ns87415"

#define DRV_VERSION "0.0.1"

​

/**

 *  ns87415_set_mode - Initialize host controller mode timings

 *  @ap: Port whose timings we are configuring

 *  @adev: Device whose timings we are configuring

 *  @mode: Mode to set

 *

 *  Program the mode registers for this controller, channel and

 *  device. Because the chip is quite an old design we have to do this

 *  for PIO/DMA switches.

 *

 *  LOCKING:

 *  None (inherited from caller).

 */

​

static void ns87415_set_mode(struct ata_port *ap, struct ata_device *adev, u8 mode)

{

    struct pci_dev *dev = to_pci_dev(ap->host->dev);

    int unit        = 2 * ap->port_no + adev->devno;

    int timing      = 0x44 + 2 * unit;

    unsigned long T     = 1000000000 / 33333;   /* PCI clocks */

    struct ata_timing t;

    u16 clocking;

    u8 iordy;

    u8 status;

​

    /* Timing register format is 17 - low nybble read timing with