linux-imx

/*

 * Calxeda Highbank AHCI SATA platform driver

 * Copyright 2012 Calxeda, Inc.

 *

 * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms and conditions of the GNU General Public License,

 * version 2, as published by the Free Software Foundation.

 *

 * This program is distributed in the hope it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

 * more details.

 *

 * You should have received a copy of the GNU General Public License along with

 * this program.  If not, see <http://www.gnu.org/licenses/>.

 */

#include <linux/kernel.h>

#include <linux/gfp.h>

#include <linux/module.h>

#include <linux/types.h>

#include <linux/err.h>

#include <linux/io.h>

#include <linux/spinlock.h>

#include <linux/device.h>

#include <linux/of_device.h>

#include <linux/of_address.h>

#include <linux/platform_device.h>

#include <linux/libata.h>

#include <linux/interrupt.h>

#include <linux/delay.h>

#include <linux/export.h>

#include <linux/gpio/consumer.h>

​

#include "ahci.h"

​

#define CPHY_MAP(dev, addr) ((((dev) & 0x1f) << 7) | (((addr) >> 9) & 0x7f))

#define CPHY_ADDR(addr) (((addr) & 0x1ff) << 2)

#define SERDES_CR_CTL           0x80a0

#define SERDES_CR_ADDR          0x80a1

#define SERDES_CR_DATA          0x80a2

#define CR_BUSY             0x0001

#define CR_START            0x0001

#define CR_WR_RDN           0x0002

#define CPHY_TX_INPUT_STS       0x2001

#define CPHY_RX_INPUT_STS       0x2002

#define CPHY_SATA_TX_OVERRIDE       0x8000

#define CPHY_SATA_RX_OVERRIDE       0x4000

#define CPHY_TX_OVERRIDE        0x2004

#define CPHY_RX_OVERRIDE        0x2005

#define SPHY_LANE           0x100

#define SPHY_HALF_RATE          0x0001

#define CPHY_SATA_DPLL_MODE     0x0700

#define CPHY_SATA_DPLL_SHIFT        8

#define CPHY_SATA_DPLL_RESET        (1 << 11)

#define CPHY_SATA_TX_ATTEN      0x1c00

#define CPHY_SATA_TX_ATTEN_SHIFT    10

#define CPHY_PHY_COUNT          6

#define CPHY_LANE_COUNT         4

#define CPHY_PORT_COUNT         (CPHY_PHY_COUNT * CPHY_LANE_COUNT)

​

static DEFINE_SPINLOCK(cphy_lock);

/* Each of the 6 phys can have up to 4 sata ports attached to i. Map 0-based

 * sata ports to their phys and then to their lanes within the phys

 */

struct phy_lane_info {

    void __iomem *phy_base;

    u8 lane_mapping;

    u8 phy_devs;

    u8 tx_atten;

};

static struct phy_lane_info port_data[CPHY_PORT_COUNT];

​

static DEFINE_SPINLOCK(sgpio_lock);

#define SCLOCK              0

#define SLOAD               1

#define SDATA               2

#define SGPIO_PINS          3

#define SGPIO_PORTS         8

​

struct ecx_plat_data {

    u32     n_ports;

    /* number of extra clocks that the SGPIO PIC controller expects */

    u32     pre_clocks;

    u32     post_clocks;

    struct gpio_desc *sgpio_gpiod[SGPIO_PINS];

    u32     sgpio_pattern;

    u32     port_to_sgpio[SGPIO_PORTS];

};

​

#define SGPIO_SIGNALS           3