linux-imx

/*

 *  sata_nv.c - NVIDIA nForce SATA

 *

 *  Copyright 2004 NVIDIA Corp.  All rights reserved.

 *  Copyright 2004 Andrew Chew

 *

 *

 *  This program is free software; you can redistribute it and/or modify

 *  it under the terms of the GNU General Public License as published by

 *  the Free Software Foundation; either version 2, or (at your option)

 *  any later version.

 *

 *  This program is distributed in the hope that it will be useful,

 *  but WITHOUT ANY WARRANTY; without even the implied warranty of

 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 *  GNU General Public License for more details.

 *

 *  You should have received a copy of the GNU General Public License

 *  along with this program; see the file COPYING.  If not, write to

 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.

 *

 *

 *  libata documentation is available via 'make {ps|pdf}docs',

 *  as Documentation/driver-api/libata.rst

 *

 *  No hardware documentation available outside of NVIDIA.

 *  This driver programs the NVIDIA SATA controller in a similar

 *  fashion as with other PCI IDE BMDMA controllers, with a few

 *  NV-specific details such as register offsets, SATA phy location,

 *  hotplug info, etc.

 *

 *  CK804/MCP04 controllers support an alternate programming interface

 *  similar to the ADMA specification (with some modifications).

 *  This allows the use of NCQ. Non-DMA-mapped ATA commands are still

 *  sent through the legacy interface.

 *

 */

​

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/gfp.h>

#include <linux/pci.h>

#include <linux/blkdev.h>

#include <linux/delay.h>

#include <linux/interrupt.h>

#include <linux/device.h>

#include <scsi/scsi_host.h>

#include <scsi/scsi_device.h>

#include <linux/libata.h>

​

#define DRV_NAME            "sata_nv"

#define DRV_VERSION         "3.5"

​

#define NV_ADMA_DMA_BOUNDARY        0xffffffffUL

​

enum {

    NV_MMIO_BAR         = 5,

​

    NV_PORTS            = 2,

    NV_PIO_MASK         = ATA_PIO4,

    NV_MWDMA_MASK           = ATA_MWDMA2,

    NV_UDMA_MASK            = ATA_UDMA6,

    NV_PORT0_SCR_REG_OFFSET     = 0x00,

    NV_PORT1_SCR_REG_OFFSET     = 0x40,

​

    /* INT_STATUS/ENABLE */

    NV_INT_STATUS           = 0x10,

    NV_INT_ENABLE           = 0x11,

    NV_INT_STATUS_CK804     = 0x440,

    NV_INT_ENABLE_CK804     = 0x441,

​

    /* INT_STATUS/ENABLE bits */

    NV_INT_DEV          = 0x01,

    NV_INT_PM           = 0x02,

    NV_INT_ADDED            = 0x04,

    NV_INT_REMOVED          = 0x08,

​

    NV_INT_PORT_SHIFT       = 4,    /* each port occupies 4 bits */

​

    NV_INT_ALL          = 0x0f,

    NV_INT_MASK         = NV_INT_DEV |

                      NV_INT_ADDED | NV_INT_REMOVED,

​

    /* INT_CONFIG */

    NV_INT_CONFIG           = 0x12,

    NV_INT_CONFIG_METHD     = 0x01, // 0 = INT, 1 = SMI

​

    // For PCI config register 20

    NV_MCP_SATA_CFG_20      = 0x50,

    NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04,

    NV_MCP_SATA_CFG_20_PORT0_EN = (1 << 17),

    NV_MCP_SATA_CFG_20_PORT1_EN = (1 << 16),