linux-imx

/*

 *  sata_qstor.c - Pacific Digital Corporation QStor SATA

 *

 *  Maintained by:  Mark Lord <mlord@pobox.com>

 *

 *  Copyright 2005 Pacific Digital Corporation.

 *  (OSL/GPL code release authorized by Jalil Fadavi).

 *

 *

 *  This program is free software; you can redistribute it and/or modify

 *  it under the terms of the GNU General Public License as published by

 *  the Free Software Foundation; either version 2, or (at your option)

 *  any later version.

 *

 *  This program is distributed in the hope that it will be useful,

 *  but WITHOUT ANY WARRANTY; without even the implied warranty of

 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 *  GNU General Public License for more details.

 *

 *  You should have received a copy of the GNU General Public License

 *  along with this program; see the file COPYING.  If not, write to

 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.

 *

 *

 *  libata documentation is available via 'make {ps|pdf}docs',

 *  as Documentation/driver-api/libata.rst

 *

 */

​

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/gfp.h>

#include <linux/pci.h>

#include <linux/blkdev.h>

#include <linux/delay.h>

#include <linux/interrupt.h>

#include <linux/device.h>

#include <scsi/scsi_host.h>

#include <linux/libata.h>

​

#define DRV_NAME    "sata_qstor"

#define DRV_VERSION "0.09"

​

enum {

    QS_MMIO_BAR     = 4,

​

    QS_PORTS        = 4,

    QS_MAX_PRD      = LIBATA_MAX_PRD,

    QS_CPB_ORDER        = 6,

    QS_CPB_BYTES        = (1 << QS_CPB_ORDER),

    QS_PRD_BYTES        = QS_MAX_PRD * 16,

    QS_PKT_BYTES        = QS_CPB_BYTES + QS_PRD_BYTES,

​

    /* global register offsets */

    QS_HCF_CNFG3        = 0x0003, /* host configuration offset */

    QS_HID_HPHY     = 0x0004, /* host physical interface info */

    QS_HCT_CTRL     = 0x00e4, /* global interrupt mask offset */

    QS_HST_SFF      = 0x0100, /* host status fifo offset */

    QS_HVS_SERD3        = 0x0393, /* PHY enable offset */

​

    /* global control bits */

    QS_HPHY_64BIT       = (1 << 1), /* 64-bit bus detected */

    QS_CNFG3_GSRST      = 0x01,     /* global chip reset */

    QS_SERD3_PHY_ENA    = 0xf0,     /* PHY detection ENAble*/

​

    /* per-channel register offsets */

    QS_CCF_CPBA     = 0x0710, /* chan CPB base address */

    QS_CCF_CSEP     = 0x0718, /* chan CPB separation factor */

    QS_CFC_HUFT     = 0x0800, /* host upstream fifo threshold */

    QS_CFC_HDFT     = 0x0804, /* host downstream fifo threshold */

    QS_CFC_DUFT     = 0x0808, /* dev upstream fifo threshold */

    QS_CFC_DDFT     = 0x080c, /* dev downstream fifo threshold */

    QS_CCT_CTR0     = 0x0900, /* chan control-0 offset */

    QS_CCT_CTR1     = 0x0901, /* chan control-1 offset */

    QS_CCT_CFF      = 0x0a00, /* chan command fifo offset */

​

    /* channel control bits */

    QS_CTR0_REG     = (1 << 1),   /* register mode (vs. pkt mode) */

    QS_CTR0_CLER        = (1 << 2),   /* clear channel errors */

    QS_CTR1_RDEV        = (1 << 1),   /* sata phy/comms reset */

    QS_CTR1_RCHN        = (1 << 4),   /* reset channel logic */

    QS_CCF_RUN_PKT      = 0x107,      /* RUN a new dma PKT */

​

    /* pkt sub-field headers */

    QS_HCB_HDR      = 0x01,   /* Host Control Block header */

    QS_DCB_HDR      = 0x02,   /* Device Control Block header */

​

    /* pkt HCB flag bits */

    QS_HF_DIRO      = (1 << 0),   /* data DIRection Out */

    QS_HF_DAT       = (1 << 3),   /* DATa pkt */

    QS_HF_IEN       = (1 << 4),   /* Interrupt ENable */

    QS_HF_VLD       = (1 << 5),   /* VaLiD pkt */