linux-imx

/* SPDX-License-Identifier: GPL-2.0 */

/* drivers/atm/midway.h - Efficient Networks Midway (SAR) description */

/* Written 1995-1999 by Werner Almesberger, EPFL LRC/ICA */

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#ifndef DRIVERS_ATM_MIDWAY_H

#define DRIVERS_ATM_MIDWAY_H

​

​

#define NR_VCI      1024        /* number of VCIs */

#define NR_VCI_LD   10      /* log2(NR_VCI) */

#define NR_DMA_RX   512     /* RX DMA queue entries */

#define NR_DMA_TX   512     /* TX DMA queue entries */

#define NR_SERVICE  NR_VCI      /* service list size */

#define NR_CHAN     8       /* number of TX channels */

#define TS_CLOCK    25000000    /* traffic shaper clock (cell/sec) */

​

#define MAP_MAX_SIZE    0x00400000  /* memory window for max config */

#define EPROM_SIZE  0x00010000

#define MEM_VALID   0xffc00000  /* mask base address with this */

#define PHY_BASE    0x00020000  /* offset of PHY register are */

#define REG_BASE    0x00040000  /* offset of Midway register area */

#define RAM_BASE    0x00200000  /* offset of RAM area */

#define RAM_INCREMENT   0x00020000  /* probe for RAM every 128kB */

​

#define MID_VCI_BASE    RAM_BASE

#define MID_DMA_RX_BASE (MID_VCI_BASE+NR_VCI*16)

#define MID_DMA_TX_BASE (MID_DMA_RX_BASE+NR_DMA_RX*8)

#define MID_SERVICE_BASE (MID_DMA_TX_BASE+NR_DMA_TX*8)

#define MID_FREE_BASE   (MID_SERVICE_BASE+NR_SERVICE*4)

​

#define MAC_LEN 6 /* atm.h */

​

#define MID_MIN_BUF_SIZE (1024)     /*   1 kB is minimum */

#define MID_MAX_BUF_SIZE (128*1024) /* 128 kB is maximum */

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#define RX_DESCR_SIZE   1       /* RX PDU descr is 1 longword */

#define TX_DESCR_SIZE   2       /* TX PDU descr is 2 longwords */

#define AAL5_TRAILER    (ATM_AAL5_TRAILER/4) /* AAL5 trailer is 2 longwords */

​

#define TX_GAP      8       /* TX buffer gap (words) */

​

/*

 * Midway Reset/ID

 *

 * All values read-only. Writing to this register resets Midway chip.

 */

​

#define MID_RES_ID_MCON 0x00        /* Midway Reset/ID */

​

#define MID_ID      0xf0000000  /* Midway version */

#define MID_SHIFT   24

#define MID_MOTHER_ID   0x00000700  /* mother board id */

#define MID_MOTHER_SHIFT 8

#define MID_CON_TI  0x00000080  /* 0: normal ctrl; 1: SABRE */

#define MID_CON_SUNI    0x00000040  /* 0: UTOPIA; 1: SUNI */

#define MID_CON_V6  0x00000020  /* 0: non-pipel UTOPIA (required iff

                       !CON_SUNI; 1: UTOPIA */

#define DAUGHTER_ID 0x0000001f  /* daughter board id */

​

/*

 * Interrupt Status Acknowledge, Interrupt Status & Interrupt Enable