linux-imx

// SPDX-License-Identifier: GPL-2.0+

/*

 * Copyright (C) 2017 Hisilicon Limited, All Rights Reserved.

 * Author: Zhichang Yuan <yuanzhichang@hisilicon.com>

 * Author: Zou Rongrong <zourongrong@huawei.com>

 * Author: John Garry <john.garry@huawei.com>

 */

​

#include <linux/acpi.h>

#include <linux/console.h>

#include <linux/delay.h>

#include <linux/io.h>

#include <linux/logic_pio.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/of_platform.h>

#include <linux/pci.h>

#include <linux/serial_8250.h>

#include <linux/slab.h>

​

#define DRV_NAME "hisi-lpc"

​

/*

 * Setting this bit means each IO operation will target a different port

 * address; 0 means repeated IO operations will use the same port,

 * such as BT.

 */

#define FG_INCRADDR_LPC     0x02

​

struct lpc_cycle_para {

    unsigned int opflags;

    unsigned int csize; /* data length of each operation */

};

​

struct hisi_lpc_dev {

    spinlock_t cycle_lock;

    void __iomem  *membase;

    struct logic_pio_hwaddr *io_host;

};

​

/* The max IO cycle counts supported is four per operation at maximum */

#define LPC_MAX_DWIDTH  4

​

#define LPC_REG_STARTUP_SIGNAL      0x00

#define LPC_REG_STARTUP_SIGNAL_START    BIT(0)

#define LPC_REG_OP_STATUS       0x04

#define LPC_REG_OP_STATUS_IDLE      BIT(0)

#define LPC_REG_OP_STATUS_FINISHED  BIT(1)

#define LPC_REG_OP_LEN          0x10 /* LPC cycles count per start */

#define LPC_REG_CMD         0x14

#define LPC_REG_CMD_OP          BIT(0) /* 0: read, 1: write */

#define LPC_REG_CMD_SAMEADDR        BIT(3)

#define LPC_REG_ADDR            0x20 /* target address */

#define LPC_REG_WDATA           0x24 /* write FIFO */

#define LPC_REG_RDATA           0x28 /* read FIFO */

​

/* The minimal nanosecond interval for each query on LPC cycle status */

#define LPC_NSEC_PERWAIT    100

​

/*

 * The maximum waiting time is about 128us.  It is specific for stream I/O,

 * such as ins.

 *

 * The fastest IO cycle time is about 390ns, but the worst case will wait

 * for extra 256 lpc clocks, so (256 + 13) * 30ns = 8 us. The maximum burst

 * cycles is 16. So, the maximum waiting time is about 128us under worst

 * case.

 *

 * Choose 1300 as the maximum.

 */

#define LPC_MAX_WAITCNT     1300

​

/* About 10us. This is specific for single IO operations, such as inb */

#define LPC_PEROP_WAITCNT   100

​

static int wait_lpc_idle(unsigned char *mbase, unsigned int waitcnt)

{

    u32 status;

​

    do {

        status = readl(mbase + LPC_REG_OP_STATUS);

        if (status & LPC_REG_OP_STATUS_IDLE)

            return (status & LPC_REG_OP_STATUS_FINISHED) ? 0 : -EIO;

        ndelay(LPC_NSEC_PERWAIT);

    } while (--waitcnt);

​

    return -ETIME;

}

​

/*

 * hisi_lpc_target_in - trigger a series of LPC cycles for read operation