linux-imx

/*

 * Address map functions for Marvell EBU SoCs (Kirkwood, Armada

 * 370/XP, Dove, Orion5x and MV78xx0)

 *

 * This file is licensed under the terms of the GNU General Public

 * License version 2.  This program is licensed "as is" without any

 * warranty of any kind, whether express or implied.

 *

 * The Marvell EBU SoCs have a configurable physical address space:

 * the physical address at which certain devices (PCIe, NOR, NAND,

 * etc.) sit can be configured. The configuration takes place through

 * two sets of registers:

 *

 * - One to configure the access of the CPU to the devices. Depending

 *   on the families, there are between 8 and 20 configurable windows,

 *   each can be use to create a physical memory window that maps to a

 *   specific device. Devices are identified by a tuple (target,

 *   attribute).

 *

 * - One to configure the access to the CPU to the SDRAM. There are

 *   either 2 (for Dove) or 4 (for other families) windows to map the

 *   SDRAM into the physical address space.

 *

 * This driver:

 *

 * - Reads out the SDRAM address decoding windows at initialization

 *   time, and fills the mvebu_mbus_dram_info structure with these

 *   informations. The exported function mv_mbus_dram_info() allow

 *   device drivers to get those informations related to the SDRAM

 *   address decoding windows. This is because devices also have their

 *   own windows (configured through registers that are part of each

 *   device register space), and therefore the drivers for Marvell

 *   devices have to configure those device -> SDRAM windows to ensure

 *   that DMA works properly.

 *

 * - Provides an API for platform code or device drivers to

 *   dynamically add or remove address decoding windows for the CPU ->

 *   device accesses. This API is mvebu_mbus_add_window_by_id(),

 *   mvebu_mbus_add_window_remap_by_id() and

 *   mvebu_mbus_del_window().

 *

 * - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to

 *   see the list of CPU -> SDRAM windows and their configuration

 *   (file 'sdram') and the list of CPU -> devices windows and their

 *   configuration (file 'devices').

 */

​

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

​

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/init.h>

#include <linux/mbus.h>

#include <linux/io.h>

#include <linux/ioport.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/debugfs.h>

#include <linux/log2.h>

#include <linux/memblock.h>

#include <linux/syscore_ops.h>

​

/*

 * DDR target is the same on all platforms.

 */

#define TARGET_DDR      0

​

/*

 * CPU Address Decode Windows registers

 */

#define WIN_CTRL_OFF        0x0000

#define   WIN_CTRL_ENABLE       BIT(0)

/* Only on HW I/O coherency capable platforms */

#define   WIN_CTRL_SYNCBARRIER  BIT(1)

#define   WIN_CTRL_TGT_MASK     0xf0

#define   WIN_CTRL_TGT_SHIFT    4

#define   WIN_CTRL_ATTR_MASK    0xff00

#define   WIN_CTRL_ATTR_SHIFT   8

#define   WIN_CTRL_SIZE_MASK    0xffff0000

#define   WIN_CTRL_SIZE_SHIFT   16

#define WIN_BASE_OFF        0x0004

#define   WIN_BASE_LOW          0xffff0000

#define   WIN_BASE_HIGH         0xf

#define WIN_REMAP_LO_OFF    0x0008

#define   WIN_REMAP_LOW         0xffff0000

#define WIN_REMAP_HI_OFF    0x000c

​

#define UNIT_SYNC_BARRIER_OFF   0x84

#define   UNIT_SYNC_BARRIER_ALL 0xFFFF

​

#define ATTR_HW_COHERENCY   (0x1 << 4)

​