linux-imx

/*

 * Qualcomm External Bus Interface 2 (EBI2) driver

 * an older version of the Qualcomm Parallel Interface Controller (QPIC)

 *

 * Copyright (C) 2016 Linaro Ltd.

 *

 * Author: Linus Walleij <linus.walleij@linaro.org>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2, as

 * published by the Free Software Foundation.

 *

 * See the device tree bindings for this block for more details on the

 * hardware.

 */

​

#include <linux/module.h>

#include <linux/clk.h>

#include <linux/err.h>

#include <linux/io.h>

#include <linux/of.h>

#include <linux/of_platform.h>

#include <linux/init.h>

#include <linux/slab.h>

#include <linux/platform_device.h>

#include <linux/bitops.h>

​

/*

 * CS0, CS1, CS4 and CS5 are two bits wide, CS2 and CS3 are one bit.

 */

#define EBI2_CS0_ENABLE_MASK BIT(0)|BIT(1)

#define EBI2_CS1_ENABLE_MASK BIT(2)|BIT(3)

#define EBI2_CS2_ENABLE_MASK BIT(4)

#define EBI2_CS3_ENABLE_MASK BIT(5)

#define EBI2_CS4_ENABLE_MASK BIT(6)|BIT(7)

#define EBI2_CS5_ENABLE_MASK BIT(8)|BIT(9)

#define EBI2_CSN_MASK GENMASK(9, 0)

​

#define EBI2_XMEM_CFG 0x0000 /* Power management etc */

​

/*

 * SLOW CSn CFG

 *

 * Bits 31-28: RECOVERY recovery cycles (0 = 1, 1 = 2 etc) this is the time the

 *             memory continues to drive the data bus after OE is de-asserted.

 *             Inserted when reading one CS and switching to another CS or read

 *             followed by write on the same CS. Valid values 0 thru 15.

 * Bits 27-24: WR_HOLD write hold cycles, these are extra cycles inserted after

 *             every write minimum 1. The data out is driven from the time WE is

 *             asserted until CS is asserted. With a hold of 1, the CS stays

 *             active for 1 extra cycle etc. Valid values 0 thru 15.

 * Bits 23-16: WR_DELTA initial latency for write cycles inserted for the first

 *             write to a page or burst memory

 * Bits 15-8:  RD_DELTA initial latency for read cycles inserted for the first

 *             read to a page or burst memory

 * Bits 7-4:   WR_WAIT number of wait cycles for every write access, 0=1 cycle

 *             so 1 thru 16 cycles.

 * Bits 3-0:   RD_WAIT number of wait cycles for every read access, 0=1 cycle

 *             so 1 thru 16 cycles.

 */

#define EBI2_XMEM_CS0_SLOW_CFG 0x0008

#define EBI2_XMEM_CS1_SLOW_CFG 0x000C

#define EBI2_XMEM_CS2_SLOW_CFG 0x0010

#define EBI2_XMEM_CS3_SLOW_CFG 0x0014

#define EBI2_XMEM_CS4_SLOW_CFG 0x0018

#define EBI2_XMEM_CS5_SLOW_CFG 0x001C

​

#define EBI2_XMEM_RECOVERY_SHIFT    28

#define EBI2_XMEM_WR_HOLD_SHIFT     24

#define EBI2_XMEM_WR_DELTA_SHIFT    16

#define EBI2_XMEM_RD_DELTA_SHIFT    8

#define EBI2_XMEM_WR_WAIT_SHIFT     4

#define EBI2_XMEM_RD_WAIT_SHIFT     0

​

/*

 * FAST CSn CFG

 * Bits 31-28: ?

 * Bits 27-24: RD_HOLD: the length in cycles of the first segment of a read

 *             transfer. For a single read trandfer this will be the time

 *             from CS assertion to OE assertion.

 * Bits 18-24: ?

 * Bits 17-16: ADV_OE_RECOVERY, the number of cycles elapsed before an OE

 *             assertion, with respect to the cycle where ADV is asserted.

 *             2 means 2 cycles between ADV and OE. Values 0, 1, 2 or 3.

 * Bits 5:     ADDR_HOLD_ENA, The address is held for an extra cycle to meet

 *             hold time requirements with ADV assertion.

 *

 * The manual mentions "write precharge cycles" and "precharge cycles".

 * We have not been able to figure out which bit fields these correspond to

 * in the hardware, or what valid values exist. The current hypothesis is that

 * this is something just used on the FAST chip selects. There is also a "byte

 * device enable" flag somewhere for 8bit memories.