linux-imx

/*

 * Intel AGPGART routines.

 */

​

#include <linux/module.h>

#include <linux/pci.h>

#include <linux/slab.h>

#include <linux/init.h>

#include <linux/kernel.h>

#include <linux/pagemap.h>

#include <linux/agp_backend.h>

#include <asm/smp.h>

#include "agp.h"

#include "intel-agp.h"

#include <drm/intel-gtt.h>

​

static int intel_fetch_size(void)

{

    int i;

    u16 temp;

    struct aper_size_info_16 *values;

​

    pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);

    values = A_SIZE_16(agp_bridge->driver->aperture_sizes);

​

    for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {

        if (temp == values[i].size_value) {

            agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);

            agp_bridge->aperture_size_idx = i;

            return values[i].size;

        }

    }

​

    return 0;

}

​

static int __intel_8xx_fetch_size(u8 temp)

{

    int i;

    struct aper_size_info_8 *values;

​

    values = A_SIZE_8(agp_bridge->driver->aperture_sizes);

​

    for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {

        if (temp == values[i].size_value) {

            agp_bridge->previous_size =

                agp_bridge->current_size = (void *) (values + i);

            agp_bridge->aperture_size_idx = i;

            return values[i].size;

        }

    }

    return 0;

}

​

static int intel_8xx_fetch_size(void)

{

    u8 temp;

​

    pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);

    return __intel_8xx_fetch_size(temp);

}

​

static int intel_815_fetch_size(void)

{

    u8 temp;

​

    /* Intel 815 chipsets have a _weird_ APSIZE register with only

     * one non-reserved bit, so mask the others out ... */

    pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);

    temp &= (1 << 3);

​

    return __intel_8xx_fetch_size(temp);

}

​

static void intel_tlbflush(struct agp_memory *mem)

{

    pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);

    pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);

}

​

​

static void intel_8xx_tlbflush(struct agp_memory *mem)

{

    u32 temp;

    pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);

    pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));

    pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);

    pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));

}

​

​

static void intel_cleanup(void)