linux-imx

/*

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 *

 * Copyright (c) 2005 Silicon Graphics, Inc.  All rights reserved.

 */

​

#ifndef __MBCS_H__

#define __MBCS_H__

​

/*

 * General macros

 */

#define MB  (1024*1024)

#define MB2 (2*MB)

#define MB4 (4*MB)

#define MB6 (6*MB)

​

/*

 * Offsets and masks

 */

#define MBCS_CM_ID      0x0000  /* Identification */

#define MBCS_CM_STATUS      0x0008  /* Status */

#define MBCS_CM_ERROR_DETAIL1   0x0010  /* Error Detail1 */

#define MBCS_CM_ERROR_DETAIL2   0x0018  /* Error Detail2 */

#define MBCS_CM_CONTROL     0x0020  /* Control */

#define MBCS_CM_REQ_TOUT    0x0028  /* Request Time-out */

#define MBCS_CM_ERR_INT_DEST    0x0038  /* Error Interrupt Destination */

#define MBCS_CM_TARG_FL     0x0050  /* Target Flush */

#define MBCS_CM_ERR_STAT    0x0060  /* Error Status */

#define MBCS_CM_CLR_ERR_STAT    0x0068  /* Clear Error Status */

#define MBCS_CM_ERR_INT_EN  0x0070  /* Error Interrupt Enable */

#define MBCS_RD_DMA_SYS_ADDR    0x0100  /* Read DMA System Address */

#define MBCS_RD_DMA_LOC_ADDR    0x0108  /* Read DMA Local Address */

#define MBCS_RD_DMA_CTRL    0x0110  /* Read DMA Control */

#define MBCS_RD_DMA_AMO_DEST    0x0118  /* Read DMA AMO Destination */

#define MBCS_RD_DMA_INT_DEST    0x0120  /* Read DMA Interrupt Destination */

#define MBCS_RD_DMA_AUX_STAT    0x0130  /* Read DMA Auxiliary Status */

#define MBCS_WR_DMA_SYS_ADDR    0x0200  /* Write DMA System Address */

#define MBCS_WR_DMA_LOC_ADDR    0x0208  /* Write DMA Local Address */

#define MBCS_WR_DMA_CTRL    0x0210  /* Write DMA Control */

#define MBCS_WR_DMA_AMO_DEST    0x0218  /* Write DMA AMO Destination */

#define MBCS_WR_DMA_INT_DEST    0x0220  /* Write DMA Interrupt Destination */

#define MBCS_WR_DMA_AUX_STAT    0x0230  /* Write DMA Auxiliary Status */

#define MBCS_ALG_AMO_DEST   0x0300  /* Algorithm AMO Destination */

#define MBCS_ALG_INT_DEST   0x0308  /* Algorithm Interrupt Destination */

#define MBCS_ALG_OFFSETS    0x0310

#define MBCS_ALG_STEP       0x0318  /* Algorithm Step */

​

#define MBCS_GSCR_START     0x0000000

#define MBCS_DEBUG_START    0x0100000

#define MBCS_RAM0_START     0x0200000

#define MBCS_RAM1_START     0x0400000

#define MBCS_RAM2_START     0x0600000

​

#define MBCS_CM_CONTROL_REQ_TOUT_MASK 0x0000000000ffffffUL

//#define PIO_BASE_ADDR_BASE_OFFSET_MASK 0x00fffffffff00000UL

​

#define MBCS_SRAM_SIZE      (1024*1024)

#define MBCS_CACHELINE_SIZE 128

​

/*

 * MMR get's and put's

 */

#define MBCS_MMR_ADDR(mmr_base, offset)((uint64_t *)(mmr_base + offset))

#define MBCS_MMR_SET(mmr_base, offset, value) {         \

    uint64_t *mbcs_mmr_set_u64p, readback;              \

    mbcs_mmr_set_u64p = (uint64_t *)(mmr_base + offset);    \

    *mbcs_mmr_set_u64p = value;                 \

    readback = *mbcs_mmr_set_u64p; \

}

#define MBCS_MMR_GET(mmr_base, offset) *(uint64_t *)(mmr_base + offset)

#define MBCS_MMR_ZERO(mmr_base, offset) MBCS_MMR_SET(mmr_base, offset, 0)

​

/*

 * MBCS mmr structures

 */

union cm_id {

    uint64_t cm_id_reg;

    struct {

        uint64_t always_one:1,  // 0

         mfg_id:11, // 11:1

         part_num:16,   // 27:12

         bitstream_rev:8,   // 35:28

        :28;        // 63:36

    };

};

​

union cm_status {

    uint64_t cm_status_reg;

    struct {