linux-imx

// SPDX-License-Identifier: GPL-2.0+

​

#define pr_fmt(fmt) "clk-aspeed: " fmt

​

#include <linux/clk-provider.h>

#include <linux/mfd/syscon.h>

#include <linux/of_address.h>

#include <linux/of_device.h>

#include <linux/platform_device.h>

#include <linux/regmap.h>

#include <linux/reset-controller.h>

#include <linux/slab.h>

#include <linux/spinlock.h>

​

#include <dt-bindings/clock/aspeed-clock.h>

​

#define ASPEED_NUM_CLKS     36

​

#define ASPEED_RESET2_OFFSET    32

​

#define ASPEED_RESET_CTRL   0x04

#define ASPEED_CLK_SELECTION    0x08

#define ASPEED_CLK_STOP_CTRL    0x0c

#define ASPEED_MPLL_PARAM   0x20

#define ASPEED_HPLL_PARAM   0x24

#define  AST2500_HPLL_BYPASS_EN BIT(20)

#define  AST2400_HPLL_PROGRAMMED BIT(18)

#define  AST2400_HPLL_BYPASS_EN BIT(17)

#define ASPEED_MISC_CTRL    0x2c

#define  UART_DIV13_EN      BIT(12)

#define ASPEED_STRAP        0x70

#define  CLKIN_25MHZ_EN     BIT(23)

#define  AST2400_CLK_SOURCE_SEL BIT(18)

#define ASPEED_CLK_SELECTION_2  0xd8

#define ASPEED_RESET_CTRL2  0xd4

​

/* Globally visible clocks */

static DEFINE_SPINLOCK(aspeed_clk_lock);

​

/* Keeps track of all clocks */

static struct clk_hw_onecell_data *aspeed_clk_data;

​

static void __iomem *scu_base;

​

/**

 * struct aspeed_gate_data - Aspeed gated clocks

 * @clock_idx: bit used to gate this clock in the clock register

 * @reset_idx: bit used to reset this IP in the reset register. -1 if no

 *             reset is required when enabling the clock

 * @name: the clock name

 * @parent_name: the name of the parent clock

 * @flags: standard clock framework flags

 */

struct aspeed_gate_data {

    u8      clock_idx;

    s8      reset_idx;

    const char  *name;

    const char  *parent_name;

    unsigned long   flags;

};

​

/**

 * struct aspeed_clk_gate - Aspeed specific clk_gate structure