linux-imx

/*

 * drivers/clk/clk-axm5516.c

 *

 * Provides clock implementations for three different types of clock devices on

 * the Axxia device: PLL clock, a clock divider and a clock mux.

 *

 * Copyright (C) 2014 LSI Corporation

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 as published by

 * the Free Software Foundation.

 */

#include <linux/module.h>

#include <linux/kernel.h>

#include <linux/slab.h>

#include <linux/platform_device.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/clk-provider.h>

#include <linux/regmap.h>

#include <dt-bindings/clock/lsi,axm5516-clks.h>

​

​

/**

 * struct axxia_clk - Common struct to all Axxia clocks.

 * @hw: clk_hw for the common clk framework

 * @regmap: Regmap for the clock control registers

 */

struct axxia_clk {

    struct clk_hw hw;

    struct regmap *regmap;

};

#define to_axxia_clk(_hw) container_of(_hw, struct axxia_clk, hw)

​

/**

 * struct axxia_pllclk - Axxia PLL generated clock.

 * @aclk: Common struct

 * @reg: Offset into regmap for PLL control register

 */

struct axxia_pllclk {

    struct axxia_clk aclk;

    u32 reg;

};

#define to_axxia_pllclk(_aclk) container_of(_aclk, struct axxia_pllclk, aclk)

​

/**

 * axxia_pllclk_recalc - Calculate the PLL generated clock rate given the

 * parent clock rate.

 */

static unsigned long

axxia_pllclk_recalc(struct clk_hw *hw, unsigned long parent_rate)

{

    struct axxia_clk *aclk = to_axxia_clk(hw);

    struct axxia_pllclk *pll = to_axxia_pllclk(aclk);

    unsigned long rate, fbdiv, refdiv, postdiv;

    u32 control;

​

    regmap_read(aclk->regmap, pll->reg, &control);

    postdiv = ((control >> 0) & 0xf) + 1;

    fbdiv   = ((control >> 4) & 0xfff) + 3;

    refdiv  = ((control >> 16) & 0x1f) + 1;

    rate = (parent_rate / (refdiv * postdiv)) * fbdiv;

​