#include <linux/clk-provider.h>
#include <linux/interrupt.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/rational.h>
#include <linux/regmap.h>
#define CDCE706_CLKIN_CLOCK 10
#define CDCE706_CLKIN_SOURCE 11
#define CDCE706_PLL_M_LOW(pll) (1 + 3 * (pll))
#define CDCE706_PLL_N_LOW(pll) (2 + 3 * (pll))
#define CDCE706_PLL_HI(pll) (3 + 3 * (pll))
#define CDCE706_PLL_MUX 3
#define CDCE706_PLL_FVCO 6
#define CDCE706_DIVIDER(div) (13 + (div))
#define CDCE706_CLKOUT(out) (19 + (out))
#define CDCE706_CLKIN_CLOCK_MASK 0x10
#define CDCE706_CLKIN_SOURCE_SHIFT 6
#define CDCE706_CLKIN_SOURCE_MASK 0xc0
#define CDCE706_CLKIN_SOURCE_LVCMOS 0x40
#define CDCE706_PLL_MUX_MASK(pll) (0x80 >> (pll))
#define CDCE706_PLL_LOW_M_MASK 0xff
#define CDCE706_PLL_LOW_N_MASK 0xff
#define CDCE706_PLL_HI_M_MASK 0x1
#define CDCE706_PLL_HI_N_MASK 0x1e
#define CDCE706_PLL_HI_N_SHIFT 1
#define CDCE706_PLL_M_MAX 0x1ff
#define CDCE706_PLL_N_MAX 0xfff
#define CDCE706_PLL_FVCO_MASK(pll) (0x80 >> (pll))
#define CDCE706_PLL_FREQ_MIN 80000000
#define CDCE706_PLL_FREQ_MAX 300000000
#define CDCE706_PLL_FREQ_HI 180000000
#define CDCE706_DIVIDER_PLL(div) (9 + (div) - ((div) > 2) - ((div) > 4))
#define CDCE706_DIVIDER_PLL_SHIFT(div) ((div) < 2 ? 5 : 3 * ((div) & 1))
#define CDCE706_DIVIDER_PLL_MASK(div) (0x7 << CDCE706_DIVIDER_PLL_SHIFT(div))
#define CDCE706_DIVIDER_DIVIDER_MASK 0x7f
#define CDCE706_DIVIDER_DIVIDER_MAX 0x7f
#define CDCE706_CLKOUT_DIVIDER_MASK 0x7
#define CDCE706_CLKOUT_ENABLE_MASK 0x8
static const struct regmap_config cdce706_regmap_config = {