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committed e1bd55e5a56// SPDX-License-Identifier: GPL-2.0/* * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com> * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org> * * Gated clock implementation *//** * DOC: basic gatable clock which can gate and ungate it's ouput * * Traits of this clock: * prepare - clk_(un)prepare only ensures parent is (un)prepared * enable - clk_enable and clk_disable are functional & control gating * rate - inherits rate from parent. No clk_set_rate support * parent - fixed parent. No clk_set_parent support *//* * It works on following logic: * * For enabling clock, enable = 1 * set2dis = 1 -> clear bit -> set = 0 * set2dis = 0 -> set bit -> set = 1 * * For disabling clock, enable = 0 * set2dis = 1 -> set bit -> set = 1 * set2dis = 0 -> clear bit -> set = 0 * * So, result is always: enable xor set2dis. */static void clk_gate_endisable(struct clk_hw *hw, int enable){ struct clk_gate *gate = to_clk_gate(hw); int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; unsigned long uninitialized_var(flags); u32 reg; set ^= enable; if (gate->lock) spin_lock_irqsave(gate->lock, flags); else __acquire(gate->lock); if (gate->flags & CLK_GATE_HIWORD_MASK) { reg = BIT(gate->bit_idx + 16); if (set) reg |= BIT(gate->bit_idx); } else { reg = clk_readl(gate->reg); if (set) reg |= BIT(gate->bit_idx); else reg &= ~BIT(gate->bit_idx); } clk_writel(reg, gate->reg); if (gate->lock) spin_unlock_irqrestore(gate->lock, flags); else __release(gate->lock);}static int clk_gate_enable(struct clk_hw *hw){ clk_gate_endisable(hw, 1); return 0;}static void clk_gate_disable(struct clk_hw *hw){ clk_gate_endisable(hw, 0);}int clk_gate_is_enabled(struct clk_hw *hw){ u32 reg; struct clk_gate *gate = to_clk_gate(hw); reg = clk_readl(gate->reg);