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struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name,// SPDX-License-Identifier: GPL-2.0/* * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org> * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org> * * Simple multiplexer clock implementation *//* * DOC: basic adjustable multiplexer clock that cannot gate * * Traits of this clock: * prepare - clk_prepare only ensures that parents are prepared * enable - clk_enable only ensures that parents are enabled * rate - rate is only affected by parent switching. No clk_set_rate support * parent - parent is adjustable through clk_set_parent */int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags, unsigned int val){ int num_parents = clk_hw_get_num_parents(hw); if (table) { int i; for (i = 0; i < num_parents; i++) if (table[i] == val) return i; return -EINVAL; } if (val && (flags & CLK_MUX_INDEX_BIT)) val = ffs(val) - 1; if (val && (flags & CLK_MUX_INDEX_ONE)) val--; if (val >= num_parents) return -EINVAL; return val;}EXPORT_SYMBOL_GPL(clk_mux_val_to_index);unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index){ unsigned int val = index; if (table) { val = table[index]; } else { if (flags & CLK_MUX_INDEX_BIT) val = 1 << index; if (flags & CLK_MUX_INDEX_ONE) val++; } return val;}EXPORT_SYMBOL_GPL(clk_mux_index_to_val);static u8 clk_mux_get_parent(struct clk_hw *hw){ struct clk_mux *mux = to_clk_mux(hw); u32 val; val = clk_readl(mux->reg) >> mux->shift; val &= mux->mask; return clk_mux_val_to_index(hw, mux->table, mux->flags, val);}static int clk_mux_set_parent(struct clk_hw *hw, u8 index){ struct clk_mux *mux = to_clk_mux(hw); u32 val = clk_mux_index_to_val(mux->table, mux->flags, index); unsigned long flags = 0; u32 reg; if (mux->lock) spin_lock_irqsave(mux->lock, flags); else __acquire(mux->lock);