linux-imx

/*

 * clk-xgene.c - AppliedMicro X-Gene Clock Interface

 *

 * Copyright (c) 2013, Applied Micro Circuits Corporation

 * Author: Loc Ho <lho@apm.com>

 *

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public License as

 * published by the Free Software Foundation; either version 2 of

 * the License, or (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,

 * MA 02111-1307 USA

 *

 */

#include <linux/module.h>

#include <linux/spinlock.h>

#include <linux/io.h>

#include <linux/of.h>

#include <linux/clkdev.h>

#include <linux/clk-provider.h>

#include <linux/of_address.h>

​

/* Register SCU_PCPPLL bit fields */

#define N_DIV_RD(src)           ((src) & 0x000001ff)

#define SC_N_DIV_RD(src)        ((src) & 0x0000007f)

#define SC_OUTDIV2(src)         (((src) & 0x00000100) >> 8)

​

/* Register SCU_SOCPLL bit fields */

#define CLKR_RD(src)            (((src) & 0x07000000)>>24)

#define CLKOD_RD(src)           (((src) & 0x00300000)>>20)

#define REGSPEC_RESET_F1_MASK       0x00010000

#define CLKF_RD(src)            (((src) & 0x000001ff))

​

#define XGENE_CLK_DRIVER_VER        "0.1"

​

static DEFINE_SPINLOCK(clk_lock);

​

static inline u32 xgene_clk_read(void __iomem *csr)

{

    return readl_relaxed(csr);

}

​

static inline void xgene_clk_write(u32 data, void __iomem *csr)

{

    writel_relaxed(data, csr);

}

​

/* PLL Clock */

enum xgene_pll_type {

    PLL_TYPE_PCP = 0,

    PLL_TYPE_SOC = 1,

};

​

struct xgene_clk_pll {

    struct clk_hw   hw;

    void __iomem    *reg;

    spinlock_t  *lock;

    u32     pll_offset;

    enum xgene_pll_type type;

    int     version;

};

​

#define to_xgene_clk_pll(_hw) container_of(_hw, struct xgene_clk_pll, hw)

​

static int xgene_clk_pll_is_enabled(struct clk_hw *hw)

{

    struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw);

    u32 data;

​

    data = xgene_clk_read(pllclk->reg + pllclk->pll_offset);

    pr_debug("%s pll %s\n", clk_hw_get_name(hw),

        data & REGSPEC_RESET_F1_MASK ? "disabled" : "enabled");

​

    return data & REGSPEC_RESET_F1_MASK ? 0 : 1;

}

​

static unsigned long xgene_clk_pll_recalc_rate(struct clk_hw *hw,

                unsigned long parent_rate)

{

    struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw);

    unsigned long fref;

    unsigned long fvco;

    u32 pll;

    u32 nref;