linux-imx

// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (C) 2016 Freescale Semiconductor, Inc.

 * Copyright 2017-2018 NXP.

 */

​

#include <dt-bindings/clock/imx6sll-clock.h>

#include <linux/clk.h>

#include <linux/clkdev.h>

#include <linux/err.h>

#include <linux/init.h>

#include <linux/io.h>

#include <linux/of.h>

#include <linux/of_address.h>

​

#include "clk.h"

​

#define CCM_ANALOG_PLL_BYPASS       (0x1 << 16)

#define BM_CCM_CCDR_MMDC_CH0_MASK   (0x2 << 16)

#define xPLL_CLR(offset)        (offset + 0x8)

​

static const char *pll_bypass_src_sels[] = { "osc", "dummy", };

static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };

static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };

static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };

static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };

static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };

static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };

static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };

static const char *step_sels[] = { "osc", "pll2_pfd2_396m", };

static const char *pll1_sw_sels[] = { "pll1_sys", "step", };

static const char *axi_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_540m", };

static const char *axi_sels[] = {"periph", "axi_alt_sel", };

static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };

static const char *periph2_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll4_audio_div", };

static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", };

static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "osc", };

static const char *periph_sels[] = { "periph_pre", "periph_clk2", };

static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", };

static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };

static const char *ssi_sels[] = {"pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", "dummy",};

static const char *spdif_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll5_video_div", "pll3_usb_otg", };

static const char *ldb_di0_div_sels[] = { "ldb_di0_div_3_5", "ldb_di0_div_7", };

static const char *ldb_di1_div_sels[] = { "ldb_di1_div_3_5", "ldb_di1_div_7", };

static const char *ldb_di0_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_pfd3_594m", "pll2_pfd1_594m", "pll3_pfd3_454m", };

static const char *ldb_di1_sels[] = { "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_bus", "pll3_pfd3_454m", "pll3_pfd2_508m", };

static const char *lcdif_pre_sels[] = { "pll2_bus", "pll3_pfd3_454m", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd1_594m", "pll3_pfd1_540m", };

static const char *ecspi_sels[] = { "pll3_60m", "osc", };

static const char *uart_sels[] = { "pll3_80m", "osc", };

static const char *perclk_sels[] = { "ipg", "osc", };

static const char *lcdif_sels[] = { "lcdif_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };

​

static const char *epdc_pre_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd2_508m", };

static const char *epdc_sels[] = { "epdc_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };

​

static struct clk *clks[IMX6SLL_CLK_END];

static struct clk_onecell_data clk_data;

​

static const struct clk_div_table post_div_table[] = {

    { .val = 2, .div = 1, },

    { .val = 1, .div = 2, },

    { .val = 0, .div = 4, },

    { }

};

​

static const struct clk_div_table video_div_table[] = {

    { .val = 0, .div = 1, },

    { .val = 1, .div = 2, },

    { .val = 2, .div = 1, },

    { .val = 3, .div = 4, },

    { }

};

​

static u32 share_count_audio;

static u32 share_count_ssi1;

static u32 share_count_ssi2;

static u32 share_count_ssi3;

​

static void __init imx6sll_clocks_init(struct device_node *ccm_node)

{

    struct device_node *np;

    void __iomem *base;

​

    clks[IMX6SLL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);

​

    clks[IMX6SLL_CLK_CKIL] = of_clk_get_by_name(ccm_node, "ckil");

    clks[IMX6SLL_CLK_OSC] = of_clk_get_by_name(ccm_node, "osc");

​

    /* ipp_di clock is external input */

    clks[IMX6SLL_CLK_IPP_DI0] = of_clk_get_by_name(ccm_node, "ipp_di0");

    clks[IMX6SLL_CLK_IPP_DI1] = of_clk_get_by_name(ccm_node, "ipp_di1");

​