linux-imx

/*

 * Purna Chandra Mandal,<purna.mandal@microchip.com>

 * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.

 *

 * This program is free software; you can distribute it and/or modify it

 * under the terms of the GNU General Public License (Version 2) as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * for more details.

 */

#include <linux/clk-provider.h>

#include <linux/delay.h>

#include <linux/device.h>

#include <linux/interrupt.h>

#include <linux/iopoll.h>

#include <asm/mach-pic32/pic32.h>

#include <asm/traps.h>

​

#include "clk-core.h"

​

/* OSCCON Reg fields */

#define OSC_CUR_MASK        0x07

#define OSC_CUR_SHIFT       12

#define OSC_NEW_MASK        0x07

#define OSC_NEW_SHIFT       8

#define OSC_SWEN        BIT(0)

​

/* SPLLCON Reg fields */

#define PLL_RANGE_MASK      0x07

#define PLL_RANGE_SHIFT     0

#define PLL_ICLK_MASK       0x01

#define PLL_ICLK_SHIFT      7

#define PLL_IDIV_MASK       0x07

#define PLL_IDIV_SHIFT      8

#define PLL_ODIV_MASK       0x07

#define PLL_ODIV_SHIFT      24

#define PLL_MULT_MASK       0x7F

#define PLL_MULT_SHIFT      16

#define PLL_MULT_MAX        128

#define PLL_ODIV_MIN        1

#define PLL_ODIV_MAX        5

​

/* Peripheral Bus Clock Reg Fields */

#define PB_DIV_MASK     0x7f

#define PB_DIV_SHIFT        0

#define PB_DIV_READY        BIT(11)

#define PB_DIV_ENABLE       BIT(15)

#define PB_DIV_MAX      128

#define PB_DIV_MIN      0

​

/* Reference Oscillator Control Reg fields */

#define REFO_SEL_MASK       0x0f

#define REFO_SEL_SHIFT      0

#define REFO_ACTIVE     BIT(8)

#define REFO_DIVSW_EN       BIT(9)

#define REFO_OE         BIT(12)

#define REFO_ON         BIT(15)

#define REFO_DIV_SHIFT      16

#define REFO_DIV_MASK       0x7fff

​

/* Reference Oscillator Trim Register Fields */

#define REFO_TRIM_REG       0x10

#define REFO_TRIM_MASK      0x1ff

#define REFO_TRIM_SHIFT     23

#define REFO_TRIM_MAX       511

​

/* Mux Slew Control Register fields */

#define SLEW_BUSY       BIT(0)

#define SLEW_DOWNEN     BIT(1)

#define SLEW_UPEN       BIT(2)

#define SLEW_DIV        0x07

#define SLEW_DIV_SHIFT      8

#define SLEW_SYSDIV     0x0f

#define SLEW_SYSDIV_SHIFT   20

​

/* Clock Poll Timeout */

#define LOCK_TIMEOUT_US         USEC_PER_MSEC

​

/* SoC specific clock needed during SPLL clock rate switch */

static struct clk_hw *pic32_sclk_hw;

​

/* add instruction pipeline delay while CPU clock is in-transition. */

#define cpu_nop5()          \

do {                    \

    __asm__ __volatile__("nop");    \

    __asm__ __volatile__("nop");    \

    __asm__ __volatile__("nop");    \

    __asm__ __volatile__("nop");    \

    __asm__ __volatile__("nop");    \