linux-imx

// SPDX-License-Identifier: GPL-2.0

/*

 * Marvell Armada XP SoC clocks

 *

 * Copyright (C) 2012 Marvell

 *

 * Gregory CLEMENT <gregory.clement@free-electrons.com>

 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

 * Andrew Lunn <andrew@lunn.ch>

 *

 */

​

#include <linux/kernel.h>

#include <linux/clk-provider.h>

#include <linux/io.h>

#include <linux/of.h>

#include "common.h"

​

/*

 * Core Clocks

 *

 * Armada XP Sample At Reset is a 64 bit bitfiled split in two

 * register of 32 bits

 */

​

#define SARL                0   /* Low part [0:31] */

#define  SARL_AXP_PCLK_FREQ_OPT     21

#define  SARL_AXP_PCLK_FREQ_OPT_MASK    0x7

#define  SARL_AXP_FAB_FREQ_OPT      24

#define  SARL_AXP_FAB_FREQ_OPT_MASK 0xF

#define SARH                4   /* High part [32:63] */

#define  SARH_AXP_PCLK_FREQ_OPT     (52-32)

#define  SARH_AXP_PCLK_FREQ_OPT_MASK    0x1

#define  SARH_AXP_PCLK_FREQ_OPT_SHIFT   3

#define  SARH_AXP_FAB_FREQ_OPT      (51-32)

#define  SARH_AXP_FAB_FREQ_OPT_MASK 0x1

#define  SARH_AXP_FAB_FREQ_OPT_SHIFT    4

​

enum { AXP_CPU_TO_NBCLK, AXP_CPU_TO_HCLK, AXP_CPU_TO_DRAMCLK };

​

static const struct coreclk_ratio axp_coreclk_ratios[] __initconst = {

    { .id = AXP_CPU_TO_NBCLK, .name = "nbclk" },

    { .id = AXP_CPU_TO_HCLK, .name = "hclk" },

    { .id = AXP_CPU_TO_DRAMCLK, .name = "dramclk" },

};

​

/* Armada XP TCLK frequency is fixed to 250MHz */

static u32 __init axp_get_tclk_freq(void __iomem *sar)

{

    return 250000000;

}

​

/* MV98DX3236 TCLK frequency is fixed to 200MHz */

static u32 __init mv98dx3236_get_tclk_freq(void __iomem *sar)

{

    return 200000000;

}

​

static const u32 axp_cpu_freqs[] __initconst = {

    1000000000,

    1066000000,

    1200000000,

    1333000000,