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committed 8d726c51282static const struct clk_gating_soc_desc dove_gating_desc[] __initconst = {// SPDX-License-Identifier: GPL-2.0/* * Marvell Dove SoC clocks * * Copyright (C) 2012 Marvell * * Gregory CLEMENT <gregory.clement@free-electrons.com> * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> * Andrew Lunn <andrew@lunn.ch> * *//* * Core Clocks * * Dove PLL sample-at-reset configuration * * SAR0[8:5] : CPU frequency * 5 = 1000 MHz * 6 = 933 MHz * 7 = 933 MHz * 8 = 800 MHz * 9 = 800 MHz * 10 = 800 MHz * 11 = 1067 MHz * 12 = 667 MHz * 13 = 533 MHz * 14 = 400 MHz * 15 = 333 MHz * others reserved. * * SAR0[11:9] : CPU to L2 Clock divider ratio * 0 = (1/1) * CPU * 2 = (1/2) * CPU * 4 = (1/3) * CPU * 6 = (1/4) * CPU * others reserved. * * SAR0[15:12] : CPU to DDR DRAM Clock divider ratio * 0 = (1/1) * CPU * 2 = (1/2) * CPU * 3 = (2/5) * CPU * 4 = (1/3) * CPU * 6 = (1/4) * CPU * 8 = (1/5) * CPU * 10 = (1/6) * CPU * 12 = (1/7) * CPU * 14 = (1/8) * CPU * 15 = (1/10) * CPU * others reserved. * * SAR0[24:23] : TCLK frequency * 0 = 166 MHz * 1 = 125 MHz * others reserved. */