linux-imx
Public
Source
committed e7beeab9c61static const struct clk_gating_soc_desc kirkwood_gating_desc[] __initconst = {// SPDX-License-Identifier: GPL-2.0/* * Marvell Kirkwood SoC clocks * * Copyright (C) 2012 Marvell * * Gregory CLEMENT <gregory.clement@free-electrons.com> * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> * Andrew Lunn <andrew@lunn.ch> * *//* * Core Clocks * * Kirkwood PLL sample-at-reset configuration * (6180 has different SAR layout than other Kirkwood SoCs) * * SAR0[4:3,22,1] : CPU frequency (6281,6292,6282) * 4 = 600 MHz * 6 = 800 MHz * 7 = 1000 MHz * 9 = 1200 MHz * 12 = 1500 MHz * 13 = 1600 MHz * 14 = 1800 MHz * 15 = 2000 MHz * others reserved. * * SAR0[19,10:9] : CPU to L2 Clock divider ratio (6281,6292,6282) * 1 = (1/2) * CPU * 3 = (1/3) * CPU * 5 = (1/4) * CPU * others reserved. * * SAR0[8:5] : CPU to DDR DRAM Clock divider ratio (6281,6292,6282) * 2 = (1/2) * CPU * 4 = (1/3) * CPU * 6 = (1/4) * CPU * 7 = (2/9) * CPU * 8 = (1/5) * CPU * 9 = (1/6) * CPU * others reserved. * * SAR0[4:2] : Kirkwood 6180 cpu/l2/ddr clock configuration (6180 only) * 5 = [CPU = 600 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/3) * CPU] * 6 = [CPU = 800 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/4) * CPU] * 7 = [CPU = 1000 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/5) * CPU] * others reserved. * * SAR0[21] : TCLK frequency * 0 = 200 MHz * 1 = 166 MHz * others reserved. */