linux-imx

/*

 * Clk driver for NXP LPC18xx/LPC43xx Clock Control Unit (CCU)

 *

 * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>

 *

 * This file is licensed under the terms of the GNU General Public

 * License version 2. This program is licensed "as is" without any

 * warranty of any kind, whether express or implied.

 */

​

#include <linux/clk.h>

#include <linux/clk-provider.h>

#include <linux/kernel.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/slab.h>

#include <linux/string.h>

​

#include <dt-bindings/clock/lpc18xx-ccu.h>

​

/* Bit defines for CCU branch configuration register */

#define LPC18XX_CCU_RUN     BIT(0)

#define LPC18XX_CCU_AUTO    BIT(1)

#define LPC18XX_CCU_DIV     BIT(5)

#define LPC18XX_CCU_DIVSTAT BIT(27)

​

/* CCU branch feature bits */

#define CCU_BRANCH_IS_BUS   BIT(0)

#define CCU_BRANCH_HAVE_DIV2    BIT(1)

​

struct lpc18xx_branch_clk_data {

    const char **name;

    int num;

};

​

struct lpc18xx_clk_branch {

    const char *base_name;

    const char *name;

    u16 offset;

    u16 flags;

    struct clk *clk;

    struct clk_gate gate;

};

​

static struct lpc18xx_clk_branch clk_branches[] = {

    {"base_apb3_clk", "apb3_bus",       CLK_APB3_BUS,       CCU_BRANCH_IS_BUS},

    {"base_apb3_clk", "apb3_i2c1",      CLK_APB3_I2C1,      0},

    {"base_apb3_clk", "apb3_dac",       CLK_APB3_DAC,       0},

    {"base_apb3_clk", "apb3_adc0",      CLK_APB3_ADC0,      0},

    {"base_apb3_clk", "apb3_adc1",      CLK_APB3_ADC1,      0},

    {"base_apb3_clk", "apb3_can0",      CLK_APB3_CAN0,      0},

​

    {"base_apb1_clk", "apb1_bus",       CLK_APB1_BUS,       CCU_BRANCH_IS_BUS},

    {"base_apb1_clk", "apb1_mc_pwm",    CLK_APB1_MOTOCON_PWM,   0},

    {"base_apb1_clk", "apb1_i2c0",      CLK_APB1_I2C0,      0},

    {"base_apb1_clk", "apb1_i2s",       CLK_APB1_I2S,       0},

    {"base_apb1_clk", "apb1_can1",      CLK_APB1_CAN1,      0},

​

    {"base_spifi_clk", "spifi",     CLK_SPIFI,      0},

​

    {"base_cpu_clk", "cpu_bus",     CLK_CPU_BUS,        CCU_BRANCH_IS_BUS},

    {"base_cpu_clk", "cpu_spifi",       CLK_CPU_SPIFI,      0},

    {"base_cpu_clk", "cpu_gpio",        CLK_CPU_GPIO,       0},

    {"base_cpu_clk", "cpu_lcd",     CLK_CPU_LCD,        0},

    {"base_cpu_clk", "cpu_ethernet",    CLK_CPU_ETHERNET,   0},

    {"base_cpu_clk", "cpu_usb0",        CLK_CPU_USB0,       0},

    {"base_cpu_clk", "cpu_emc",     CLK_CPU_EMC,        0},

    {"base_cpu_clk", "cpu_sdio",        CLK_CPU_SDIO,       0},

    {"base_cpu_clk", "cpu_dma",     CLK_CPU_DMA,        0},

    {"base_cpu_clk", "cpu_core",        CLK_CPU_CORE,       0},

    {"base_cpu_clk", "cpu_sct",     CLK_CPU_SCT,        0},

    {"base_cpu_clk", "cpu_usb1",        CLK_CPU_USB1,       0},

    {"base_cpu_clk", "cpu_emcdiv",      CLK_CPU_EMCDIV,     CCU_BRANCH_HAVE_DIV2},

    {"base_cpu_clk", "cpu_flasha",      CLK_CPU_FLASHA,     CCU_BRANCH_HAVE_DIV2},

    {"base_cpu_clk", "cpu_flashb",      CLK_CPU_FLASHB,     CCU_BRANCH_HAVE_DIV2},

    {"base_cpu_clk", "cpu_m0app",       CLK_CPU_M0APP,      CCU_BRANCH_HAVE_DIV2},

    {"base_cpu_clk", "cpu_adchs",       CLK_CPU_ADCHS,      CCU_BRANCH_HAVE_DIV2},

    {"base_cpu_clk", "cpu_eeprom",      CLK_CPU_EEPROM,     CCU_BRANCH_HAVE_DIV2},

    {"base_cpu_clk", "cpu_wwdt",        CLK_CPU_WWDT,       0},

    {"base_cpu_clk", "cpu_uart0",       CLK_CPU_UART0,      0},

    {"base_cpu_clk", "cpu_uart1",       CLK_CPU_UART1,      0},

    {"base_cpu_clk", "cpu_ssp0",        CLK_CPU_SSP0,       0},

    {"base_cpu_clk", "cpu_timer0",      CLK_CPU_TIMER0,     0},

    {"base_cpu_clk", "cpu_timer1",      CLK_CPU_TIMER1,     0},

    {"base_cpu_clk", "cpu_scu",     CLK_CPU_SCU,        0},

    {"base_cpu_clk", "cpu_creg",        CLK_CPU_CREG,       0},

    {"base_cpu_clk", "cpu_ritimer",     CLK_CPU_RITIMER,    0},

    {"base_cpu_clk", "cpu_uart2",       CLK_CPU_UART2,      0},

    {"base_cpu_clk", "cpu_uart3",       CLK_CPU_UART3,      0},

    {"base_cpu_clk", "cpu_timer2",      CLK_CPU_TIMER2,     0},

    {"base_cpu_clk", "cpu_timer3",      CLK_CPU_TIMER3,     0},

    {"base_cpu_clk", "cpu_ssp1",        CLK_CPU_SSP1,       0},