linux-imx

/*

 * Clk driver for NXP LPC18xx/LPC43xx Clock Generation Unit (CGU)

 *

 * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>

 *

 * This file is licensed under the terms of the GNU General Public

 * License version 2. This program is licensed "as is" without any

 * warranty of any kind, whether express or implied.

 */

​

#include <linux/clk-provider.h>

#include <linux/delay.h>

#include <linux/kernel.h>

#include <linux/of.h>

#include <linux/of_address.h>

​

#include <dt-bindings/clock/lpc18xx-cgu.h>

​

/* Clock Generation Unit (CGU) registers */

#define LPC18XX_CGU_XTAL_OSC_CTRL   0x018

#define LPC18XX_CGU_PLL0USB_STAT    0x01c

#define LPC18XX_CGU_PLL0USB_CTRL    0x020

#define LPC18XX_CGU_PLL0USB_MDIV    0x024

#define LPC18XX_CGU_PLL0USB_NP_DIV  0x028

#define LPC18XX_CGU_PLL0AUDIO_STAT  0x02c

#define LPC18XX_CGU_PLL0AUDIO_CTRL  0x030

#define LPC18XX_CGU_PLL0AUDIO_MDIV  0x034

#define LPC18XX_CGU_PLL0AUDIO_NP_DIV    0x038

#define LPC18XX_CGU_PLL0AUDIO_FRAC  0x03c

#define LPC18XX_CGU_PLL1_STAT       0x040

#define LPC18XX_CGU_PLL1_CTRL       0x044

#define  LPC18XX_PLL1_CTRL_FBSEL    BIT(6)

#define  LPC18XX_PLL1_CTRL_DIRECT   BIT(7)

#define LPC18XX_CGU_IDIV_CTRL(n)    (0x048 + (n) * sizeof(u32))

#define LPC18XX_CGU_BASE_CLK(id)    (0x05c + (id) * sizeof(u32))

#define LPC18XX_CGU_PLL_CTRL_OFFSET 0x4

​

/* PLL0 bits common to both audio and USB PLL */

#define LPC18XX_PLL0_STAT_LOCK      BIT(0)

#define LPC18XX_PLL0_CTRL_PD        BIT(0)

#define LPC18XX_PLL0_CTRL_BYPASS    BIT(1)

#define LPC18XX_PLL0_CTRL_DIRECTI   BIT(2)

#define LPC18XX_PLL0_CTRL_DIRECTO   BIT(3)

#define LPC18XX_PLL0_CTRL_CLKEN     BIT(4)

#define LPC18XX_PLL0_MDIV_MDEC_MASK 0x1ffff

#define LPC18XX_PLL0_MDIV_SELP_SHIFT    17

#define LPC18XX_PLL0_MDIV_SELI_SHIFT    22

#define LPC18XX_PLL0_MSEL_MAX       BIT(15)

​

/* Register value that gives PLL0 post/pre dividers equal to 1 */

#define LPC18XX_PLL0_NP_DIVS_1      0x00302062

​

enum {

    CLK_SRC_OSC32,

    CLK_SRC_IRC,

    CLK_SRC_ENET_RX_CLK,

    CLK_SRC_ENET_TX_CLK,

    CLK_SRC_GP_CLKIN,

    CLK_SRC_RESERVED1,

    CLK_SRC_OSC,

    CLK_SRC_PLL0USB,

    CLK_SRC_PLL0AUDIO,

    CLK_SRC_PLL1,