linux-imx

/*

 * Clk driver for NXP LPC18xx/43xx Configuration Registers (CREG)

 *

 * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>

 *

 * This file is licensed under the terms of the GNU General Public

 * License version 2. This program is licensed "as is" without any

 * warranty of any kind, whether express or implied.

 */

​

#include <linux/clk-provider.h>

#include <linux/delay.h>

#include <linux/kernel.h>

#include <linux/mfd/syscon.h>

#include <linux/of.h>

#include <linux/platform_device.h>

#include <linux/regmap.h>

​

#define LPC18XX_CREG_CREG0          0x004

#define  LPC18XX_CREG_CREG0_EN1KHZ      BIT(0)

#define  LPC18XX_CREG_CREG0_EN32KHZ     BIT(1)

#define  LPC18XX_CREG_CREG0_RESET32KHZ      BIT(2)

#define  LPC18XX_CREG_CREG0_PD32KHZ     BIT(3)

​

#define to_clk_creg(_hw) container_of(_hw, struct clk_creg_data, hw)

​

enum {

    CREG_CLK_1KHZ,

    CREG_CLK_32KHZ,

    CREG_CLK_MAX,

};

​

struct clk_creg_data {

    struct clk_hw hw;

    const char *name;

    struct regmap *reg;

    unsigned int en_mask;

    const struct clk_ops *ops;

};

​

#define CREG_CLK(_name, _emask, _ops)       \

{                       \

    .name = _name,              \

    .en_mask = LPC18XX_CREG_CREG0_##_emask, \

    .ops = &_ops,               \

}

​

static int clk_creg_32k_prepare(struct clk_hw *hw)

{

    struct clk_creg_data *creg = to_clk_creg(hw);

    int ret;

​

    ret = regmap_update_bits(creg->reg, LPC18XX_CREG_CREG0,

                 LPC18XX_CREG_CREG0_PD32KHZ |

                 LPC18XX_CREG_CREG0_RESET32KHZ, 0);

​

    /*

     * Powering up the 32k oscillator takes a long while

     * and sadly there aren't any status bit to poll.

     */

    msleep(2500);

​

    return ret;

}

​

static void clk_creg_32k_unprepare(struct clk_hw *hw)

{

    struct clk_creg_data *creg = to_clk_creg(hw);

​

    regmap_update_bits(creg->reg, LPC18XX_CREG_CREG0,

               LPC18XX_CREG_CREG0_PD32KHZ,

               LPC18XX_CREG_CREG0_PD32KHZ);

}

​

static int clk_creg_32k_is_prepared(struct clk_hw *hw)

{

    struct clk_creg_data *creg = to_clk_creg(hw);

    u32 reg;

​

    regmap_read(creg->reg, LPC18XX_CREG_CREG0, &reg);

​

    return !(reg & LPC18XX_CREG_CREG0_PD32KHZ) &&

           !(reg & LPC18XX_CREG_CREG0_RESET32KHZ);

}

​

static unsigned long clk_creg_1k_recalc_rate(struct clk_hw *hw,

                         unsigned long parent_rate)

{

    return parent_rate / 32;

}

​

static int clk_creg_enable(struct clk_hw *hw)