linux-imx

/*

 * Copyright 2015 Vladimir Zapolskiy <vz@mleia.com>

 *

 * The code contained herein is licensed under the GNU General Public

 * License. You may obtain a copy of the GNU General Public License

 * Version 2 or later at the following locations:

 *

 * http://www.opensource.org/licenses/gpl-license.html

 * http://www.gnu.org/copyleft/gpl.html

 */

​

#include <linux/clk.h>

#include <linux/clk-provider.h>

#include <linux/of_address.h>

#include <linux/regmap.h>

​

#include <dt-bindings/clock/lpc32xx-clock.h>

​

#undef pr_fmt

#define pr_fmt(fmt) "%s: " fmt, __func__

​

/* Common bitfield definitions for x397 PLL (lock), USB PLL and HCLK PLL */

#define PLL_CTRL_ENABLE         BIT(16)

#define PLL_CTRL_BYPASS         BIT(15)

#define PLL_CTRL_DIRECT         BIT(14)

#define PLL_CTRL_FEEDBACK       BIT(13)

#define PLL_CTRL_POSTDIV        (BIT(12)|BIT(11))

#define PLL_CTRL_PREDIV         (BIT(10)|BIT(9))

#define PLL_CTRL_FEEDDIV        (0xFF << 1)

#define PLL_CTRL_LOCK           BIT(0)

​

/* Clock registers on System Control Block */

#define LPC32XX_CLKPWR_DEBUG_CTRL   0x00

#define LPC32XX_CLKPWR_USB_DIV      0x1C

#define LPC32XX_CLKPWR_HCLKDIV_CTRL 0x40

#define LPC32XX_CLKPWR_PWR_CTRL     0x44

#define LPC32XX_CLKPWR_PLL397_CTRL  0x48

#define LPC32XX_CLKPWR_OSC_CTRL     0x4C

#define LPC32XX_CLKPWR_SYSCLK_CTRL  0x50

#define LPC32XX_CLKPWR_LCDCLK_CTRL  0x54

#define LPC32XX_CLKPWR_HCLKPLL_CTRL 0x58

#define LPC32XX_CLKPWR_ADCCLK_CTRL1 0x60

#define LPC32XX_CLKPWR_USB_CTRL     0x64

#define LPC32XX_CLKPWR_SSP_CTRL     0x78

#define LPC32XX_CLKPWR_I2S_CTRL     0x7C

#define LPC32XX_CLKPWR_MS_CTRL      0x80

#define LPC32XX_CLKPWR_MACCLK_CTRL  0x90

#define LPC32XX_CLKPWR_TEST_CLK_CTRL    0xA4

#define LPC32XX_CLKPWR_I2CCLK_CTRL  0xAC

#define LPC32XX_CLKPWR_KEYCLK_CTRL  0xB0

#define LPC32XX_CLKPWR_ADCCLK_CTRL  0xB4

#define LPC32XX_CLKPWR_PWMCLK_CTRL  0xB8

#define LPC32XX_CLKPWR_TIMCLK_CTRL  0xBC

#define LPC32XX_CLKPWR_TIMCLK_CTRL1 0xC0

#define LPC32XX_CLKPWR_SPI_CTRL     0xC4

#define LPC32XX_CLKPWR_FLASHCLK_CTRL    0xC8

#define LPC32XX_CLKPWR_UART3_CLK_CTRL   0xD0

#define LPC32XX_CLKPWR_UART4_CLK_CTRL   0xD4

#define LPC32XX_CLKPWR_UART5_CLK_CTRL   0xD8

#define LPC32XX_CLKPWR_UART6_CLK_CTRL   0xDC

#define LPC32XX_CLKPWR_IRDA_CLK_CTRL    0xE0

#define LPC32XX_CLKPWR_UART_CLK_CTRL    0xE4

#define LPC32XX_CLKPWR_DMA_CLK_CTRL 0xE8

​

/* Clock registers on USB controller */

#define LPC32XX_USB_CLK_CTRL        0xF4

#define LPC32XX_USB_CLK_STS     0xF8

​

static struct regmap_config lpc32xx_scb_regmap_config = {

    .name = "scb",

    .reg_bits = 32,

    .val_bits = 32,

    .reg_stride = 4,

    .val_format_endian = REGMAP_ENDIAN_LITTLE,

    .max_register = 0x114,

    .fast_io = true,

};

​

static struct regmap *clk_regmap;

static void __iomem *usb_clk_vbase;

​

enum {

    LPC32XX_USB_CLK_OTG = LPC32XX_USB_CLK_HOST + 1,

    LPC32XX_USB_CLK_AHB,

​

    LPC32XX_USB_CLK_MAX = LPC32XX_USB_CLK_AHB + 1,

};

​

enum {

    /* Start from the last defined clock in dt bindings */

    LPC32XX_CLK_ADC_DIV = LPC32XX_CLK_PERIPH + 1,

    LPC32XX_CLK_ADC_RTC,