linux-imx

/*

 * Marvell PXA25x family clocks

 *

 * Copyright (C) 2014 Robert Jarzmik

 *

 * Heavily inspired from former arch/arm/mach-pxa/pxa25x.c.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; version 2 of the License.

 *

 * For non-devicetree platforms. Once pxa is fully converted to devicetree, this

 * should go away.

 */

#include <linux/clk-provider.h>

#include <linux/clk.h>

#include <linux/clkdev.h>

#include <linux/io.h>

#include <linux/of.h>

#include <mach/pxa2xx-regs.h>

#include <mach/smemc.h>

​

#include <dt-bindings/clock/pxa-clock.h>

#include "clk-pxa.h"

​

#define KHz 1000

#define MHz (1000 * 1000)

​

enum {

    PXA_CORE_RUN = 0,

    PXA_CORE_TURBO,

};

​

#define PXA25x_CLKCFG(T)            \

    (CLKCFG_FCS |               \

     ((T) ? CLKCFG_TURBO : 0))

#define PXA25x_CCCR(N2, M, L) (N2 << 7 | M << 5 | L)

​

#define MDCNFG_DRAC2(mdcnfg)    (((mdcnfg) >> 21) & 0x3)

#define MDCNFG_DRAC0(mdcnfg)    (((mdcnfg) >> 5) & 0x3)

​

/* Define the refresh period in mSec for the SDRAM and the number of rows */

#define SDRAM_TREF  64  /* standard 64ms SDRAM */

​

/*

 * Various clock factors driven by the CCCR register.

 */

​

/* Crystal Frequency to Memory Frequency Multiplier (L) */

static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };

​

/* Memory Frequency to Run Mode Frequency Multiplier (M) */

static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };

​

/* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */

/* Note: we store the value N * 2 here. */

static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };

​

static const char * const get_freq_khz[] = {

    "core", "run", "cpll", "memory"

};

​

static int get_sdram_rows(void)

{

    static int sdram_rows;

    unsigned int drac2 = 0, drac0 = 0;

    u32 mdcnfg;

​

    if (sdram_rows)

        return sdram_rows;

​

    mdcnfg = readl_relaxed(MDCNFG);

​

    if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3))

        drac2 = MDCNFG_DRAC2(mdcnfg);

​

    if (mdcnfg & (MDCNFG_DE0 | MDCNFG_DE1))

        drac0 = MDCNFG_DRAC0(mdcnfg);

​

    sdram_rows = 1 << (11 + max(drac0, drac2));

    return sdram_rows;

}

​

static u32 mdrefr_dri(unsigned int freq_khz)

{

    u32 interval = freq_khz * SDRAM_TREF / get_sdram_rows();

​

    return interval / 32;

}

​

/*

 * Get the clock frequency as reflected by CCCR and the turbo flag.