linux-imx

// SPDX-License-Identifier: GPL-2.0

/*

 * r8a7740 Core CPG Clocks

 *

 * Copyright (C) 2014  Ulrich Hecht

 */

​

#include <linux/clk-provider.h>

#include <linux/clk/renesas.h>

#include <linux/init.h>

#include <linux/kernel.h>

#include <linux/slab.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/spinlock.h>

​

struct r8a7740_cpg {

    struct clk_onecell_data data;

    spinlock_t lock;

    void __iomem *reg;

};

​

#define CPG_FRQCRA  0x00

#define CPG_FRQCRB  0x04

#define CPG_PLLC2CR 0x2c

#define CPG_USBCKCR 0x8c

#define CPG_FRQCRC  0xe0

​

#define CLK_ENABLE_ON_INIT BIT(0)

​

struct div4_clk {

    const char *name;

    unsigned int reg;

    unsigned int shift;

    int flags;

};

​

static struct div4_clk div4_clks[] = {

    { "i", CPG_FRQCRA, 20, CLK_ENABLE_ON_INIT },

    { "zg", CPG_FRQCRA, 16, CLK_ENABLE_ON_INIT },

    { "b", CPG_FRQCRA,  8, CLK_ENABLE_ON_INIT },

    { "m1", CPG_FRQCRA,  4, CLK_ENABLE_ON_INIT },

    { "hp", CPG_FRQCRB,  4, 0 },

    { "hpp", CPG_FRQCRC, 20, 0 },

    { "usbp", CPG_FRQCRC, 16, 0 },

    { "s", CPG_FRQCRC, 12, 0 },

    { "zb", CPG_FRQCRC,  8, 0 },

    { "m3", CPG_FRQCRC,  4, 0 },

    { "cp", CPG_FRQCRC,  0, 0 },

    { NULL, 0, 0, 0 },

};

​

static const struct clk_div_table div4_div_table[] = {

    { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 },

    { 6, 16 }, { 7, 18 }, { 8, 24 }, { 9, 32 }, { 10, 36 }, { 11, 48 },

    { 13, 72 }, { 14, 96 }, { 0, 0 }

};

​

static u32 cpg_mode __initdata;

​

static struct clk * __init

r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg,

                 const char *name)