linux-imx

// SPDX-License-Identifier: GPL-2.0

/*

 * r8a7745 Clock Pulse Generator / Module Standby and Software Reset

 *

 * Copyright (C) 2016 Cogent Embedded Inc.

 */

​

#include <linux/device.h>

#include <linux/init.h>

#include <linux/kernel.h>

#include <linux/soc/renesas/rcar-rst.h>

​

#include <dt-bindings/clock/r8a7745-cpg-mssr.h>

​

#include "renesas-cpg-mssr.h"

#include "rcar-gen2-cpg.h"

​

enum clk_ids {

    /* Core Clock Outputs exported to DT */

    LAST_DT_CORE_CLK = R8A7745_CLK_OSC,

​

    /* External Input Clocks */

    CLK_EXTAL,

    CLK_USB_EXTAL,

​

    /* Internal Core Clocks */

    CLK_MAIN,

    CLK_PLL0,

    CLK_PLL1,

    CLK_PLL3,

    CLK_PLL1_DIV2,

​

    /* Module Clocks */

    MOD_CLK_BASE

};

​

static const struct cpg_core_clk r8a7745_core_clks[] __initconst = {

    /* External Clock Inputs */

    DEF_INPUT("extal",  CLK_EXTAL),

    DEF_INPUT("usb_extal",  CLK_USB_EXTAL),

​

    /* Internal Core Clocks */

    DEF_BASE(".main",   CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),

    DEF_BASE(".pll0",   CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),

    DEF_BASE(".pll1",   CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),

    DEF_BASE(".pll3",   CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),

​

    DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),

​

    /* Core Clock Outputs */

    DEF_BASE("sdh",  R8A7745_CLK_SDH,  CLK_TYPE_GEN2_SDH,   CLK_PLL1),

    DEF_BASE("sd0",  R8A7745_CLK_SD0,  CLK_TYPE_GEN2_SD0,   CLK_PLL1),

    DEF_BASE("qspi", R8A7745_CLK_QSPI, CLK_TYPE_GEN2_QSPI,  CLK_PLL1_DIV2),

    DEF_BASE("rcan", R8A7745_CLK_RCAN, CLK_TYPE_GEN2_RCAN,  CLK_USB_EXTAL),

​

    DEF_FIXED("z2",    R8A7745_CLK_Z2,  CLK_PLL0,       1, 1),

    DEF_FIXED("zg",    R8A7745_CLK_ZG,  CLK_PLL1,       6, 1),

    DEF_FIXED("zx",    R8A7745_CLK_ZX,  CLK_PLL1,       3, 1),

    DEF_FIXED("zs",    R8A7745_CLK_ZS,  CLK_PLL1,       6, 1),

    DEF_FIXED("hp",    R8A7745_CLK_HP,  CLK_PLL1,      12, 1),

    DEF_FIXED("b",     R8A7745_CLK_B,   CLK_PLL1,      12, 1),

    DEF_FIXED("lb",    R8A7745_CLK_LB,  CLK_PLL1,      24, 1),

    DEF_FIXED("p",     R8A7745_CLK_P,   CLK_PLL1,      24, 1),