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committed f70f4be7339x
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {// SPDX-License-Identifier: GPL-2.0/* * r8a77965 Clock Pulse Generator / Module Standby and Software Reset * * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org> * * Based on r8a7795-cpg-mssr.c * * Copyright (C) 2015 Glider bvba * Copyright (C) 2015 Renesas Electronics Corp. */enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = R8A77965_CLK_OSC, /* External Input Clocks */ CLK_EXTAL, CLK_EXTALR, /* Internal Core Clocks */ CLK_MAIN, CLK_PLL0, CLK_PLL1, CLK_PLL3, CLK_PLL4, CLK_PLL1_DIV2, CLK_PLL1_DIV4, CLK_S0, CLK_S1, CLK_S2, CLK_S3, CLK_SDSRC, CLK_SSPSRC, CLK_RINT, /* Module Clocks */ MOD_CLK_BASE};static const struct cpg_core_clk r8a77965_core_clks[] __initconst = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), DEF_INPUT("extalr", CLK_EXTALR), /* Internal Core Clocks */ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN), DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1), DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1), DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), /* Core Clock Outputs */ DEF_BASE("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0), DEF_FIXED("ztr", R8A77965_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A77965_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A77965_CLK_ZT, CLK_PLL1_DIV2, 4, 1), DEF_FIXED("zx", R8A77965_CLK_ZX, CLK_PLL1_DIV2, 2, 1), DEF_FIXED("s0d1", R8A77965_CLK_S0D1, CLK_S0, 1, 1), DEF_FIXED("s0d2", R8A77965_CLK_S0D2, CLK_S0, 2, 1), DEF_FIXED("s0d3", R8A77965_CLK_S0D3, CLK_S0, 3, 1), DEF_FIXED("s0d4", R8A77965_CLK_S0D4, CLK_S0, 4, 1), DEF_FIXED("s0d6", R8A77965_CLK_S0D6, CLK_S0, 6, 1), DEF_FIXED("s0d8", R8A77965_CLK_S0D8, CLK_S0, 8, 1), DEF_FIXED("s0d12", R8A77965_CLK_S0D12, CLK_S0, 12, 1), DEF_FIXED("s1d1", R8A77965_CLK_S1D1, CLK_S1, 1, 1), DEF_FIXED("s1d2", R8A77965_CLK_S1D2, CLK_S1, 2, 1), DEF_FIXED("s1d4", R8A77965_CLK_S1D4, CLK_S1, 4, 1), DEF_FIXED("s2d1", R8A77965_CLK_S2D1, CLK_S2, 1, 1), DEF_FIXED("s2d2", R8A77965_CLK_S2D2, CLK_S2, 2, 1), DEF_FIXED("s2d4", R8A77965_CLK_S2D4, CLK_S2, 4, 1), DEF_FIXED("s3d1", R8A77965_CLK_S3D1, CLK_S3, 1, 1),