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committed 396bc9d40d6static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[8] __initconst = {// SPDX-License-Identifier: GPL-2.0/* * r8a77970 Clock Pulse Generator / Module Standby and Software Reset * * Copyright (C) 2017-2018 Cogent Embedded Inc. * * Based on r8a7795-cpg-mssr.c * * Copyright (C) 2015 Glider bvba */enum r8a77970_clk_types { CLK_TYPE_R8A77970_SD0H = CLK_TYPE_GEN3_SOC_BASE, CLK_TYPE_R8A77970_SD0,};enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = R8A77970_CLK_OSC, /* External Input Clocks */ CLK_EXTAL, CLK_EXTALR, /* Internal Core Clocks */ CLK_MAIN, CLK_PLL0, CLK_PLL1, CLK_PLL3, CLK_PLL1_DIV2, CLK_PLL1_DIV4, /* Module Clocks */ MOD_CLK_BASE};static spinlock_t cpg_lock;static const struct clk_div_table cpg_sd0h_div_table[] = { { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 },};static const struct clk_div_table cpg_sd0_div_table[] = { { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 }, { 0, 0 },};