linux-imx

// SPDX-License-Identifier: GPL-2.0

/*

 * r8a77995 Clock Pulse Generator / Module Standby and Software Reset

 *

 * Copyright (C) 2017 Glider bvba

 *

 * Based on r8a7795-cpg-mssr.c

 *

 * Copyright (C) 2015 Glider bvba

 * Copyright (C) 2015 Renesas Electronics Corp.

 */

​

#include <linux/device.h>

#include <linux/init.h>

#include <linux/kernel.h>

#include <linux/soc/renesas/rcar-rst.h>

​

#include <dt-bindings/clock/r8a77995-cpg-mssr.h>

​

#include "renesas-cpg-mssr.h"

#include "rcar-gen3-cpg.h"

​

enum clk_ids {

    /* Core Clock Outputs exported to DT */

    LAST_DT_CORE_CLK = R8A77995_CLK_CPEX,

​

    /* External Input Clocks */

    CLK_EXTAL,

​

    /* Internal Core Clocks */

    CLK_MAIN,

    CLK_PLL0,

    CLK_PLL1,

    CLK_PLL3,

    CLK_PLL0D2,

    CLK_PLL0D3,

    CLK_PLL0D5,

    CLK_PLL1D2,

    CLK_PE,

    CLK_S0,

    CLK_S1,

    CLK_S2,

    CLK_S3,

    CLK_SDSRC,

    CLK_RINT,

    CLK_OCO,

​

    /* Module Clocks */

    MOD_CLK_BASE

};

​

static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {

    /* External Clock Inputs */

    DEF_INPUT("extal",     CLK_EXTAL),

​

    /* Internal Core Clocks */

    DEF_BASE(".main",      CLK_MAIN, CLK_TYPE_GEN3_MAIN,       CLK_EXTAL),

    DEF_BASE(".pll1",      CLK_PLL1, CLK_TYPE_GEN3_PLL1,       CLK_MAIN),

    DEF_BASE(".pll3",      CLK_PLL3, CLK_TYPE_GEN3_PLL3,       CLK_MAIN),

​

    DEF_FIXED(".pll0",     CLK_PLL0,           CLK_MAIN,       4, 250),

    DEF_FIXED(".pll0d2",   CLK_PLL0D2,         CLK_PLL0,       2, 1),

    DEF_FIXED(".pll0d3",   CLK_PLL0D3,         CLK_PLL0,       3, 1),