linux-imx

// SPDX-License-Identifier: GPL-2.0

/*

 * R-Car Gen2 Clock Pulse Generator

 *

 * Copyright (C) 2016 Cogent Embedded Inc.

 */

​

#include <linux/bug.h>

#include <linux/clk.h>

#include <linux/clk-provider.h>

#include <linux/device.h>

#include <linux/err.h>

#include <linux/init.h>

#include <linux/io.h>

#include <linux/slab.h>

#include <linux/sys_soc.h>

​

#include "renesas-cpg-mssr.h"

#include "rcar-gen2-cpg.h"

​

#define CPG_FRQCRB      0x0004

#define CPG_FRQCRB_KICK     BIT(31)

#define CPG_SDCKCR      0x0074

#define CPG_PLL0CR      0x00d8

#define CPG_PLL0CR_STC_SHIFT    24

#define CPG_PLL0CR_STC_MASK (0x7f << CPG_PLL0CR_STC_SHIFT)

#define CPG_FRQCRC      0x00e0

#define CPG_FRQCRC_ZFC_SHIFT    8

#define CPG_FRQCRC_ZFC_MASK (0x1f << CPG_FRQCRC_ZFC_SHIFT)

#define CPG_ADSPCKCR        0x025c

#define CPG_RCANCKCR        0x0270

​

static spinlock_t cpg_lock;

​

/*

 * Z Clock

 *

 * Traits of this clock:

 * prepare - clk_prepare only ensures that parents are prepared

 * enable - clk_enable only ensures that parents are enabled

 * rate - rate is adjustable.  clk->rate = parent->rate * mult / 32

 * parent - fixed parent.  No clk_set_parent support

 */

​

struct cpg_z_clk {

    struct clk_hw hw;

    void __iomem *reg;

    void __iomem *kick_reg;

};

​

#define to_z_clk(_hw)   container_of(_hw, struct cpg_z_clk, hw)

​

static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,

                       unsigned long parent_rate)

{

    struct cpg_z_clk *zclk = to_z_clk(hw);

    unsigned int mult;

    unsigned int val;

​

    val = (readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK) >> CPG_FRQCRC_ZFC_SHIFT;

    mult = 32 - val;

​

    return div_u64((u64)parent_rate * mult, 32);