linux-imx

/*

 * Copyright (c) 2013 Samsung Electronics Co., Ltd.

 * Author: Padmavathi Venna <padma.v@samsung.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * Common Clock Framework support for Audio Subsystem Clock Controller.

*/

​

#include <linux/slab.h>

#include <linux/io.h>

#include <linux/clk.h>

#include <linux/clk-provider.h>

#include <linux/of_address.h>

#include <linux/of_device.h>

#include <linux/module.h>

#include <linux/platform_device.h>

#include <linux/pm_runtime.h>

​

#include <dt-bindings/clock/exynos-audss-clk.h>

​

static DEFINE_SPINLOCK(lock);

static void __iomem *reg_base;

static struct clk_hw_onecell_data *clk_data;

/*

 * On Exynos5420 this will be a clock which has to be enabled before any

 * access to audss registers. Typically a child of EPLL.

 *

 * On other platforms this will be -ENODEV.

 */

static struct clk *epll;

​

#define ASS_CLK_SRC 0x0

#define ASS_CLK_DIV 0x4

#define ASS_CLK_GATE 0x8

​

static unsigned long reg_save[][2] = {

    { ASS_CLK_SRC,  0 },

    { ASS_CLK_DIV,  0 },

    { ASS_CLK_GATE, 0 },

};

​

static int __maybe_unused exynos_audss_clk_suspend(struct device *dev)

{

    int i;

​

    for (i = 0; i < ARRAY_SIZE(reg_save); i++)

        reg_save[i][1] = readl(reg_base + reg_save[i][0]);

​

    return 0;

}

​

static int __maybe_unused exynos_audss_clk_resume(struct device *dev)

{

    int i;

​

    for (i = 0; i < ARRAY_SIZE(reg_save); i++)

        writel(reg_save[i][1], reg_base + reg_save[i][0]);

​

    return 0;

}