linux-imx

/*

 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * Common Clock Framework support for S3C2410 and following SoCs.

 */

​

#include <linux/clk-provider.h>

#include <linux/of.h>

#include <linux/of_address.h>

​

#include <dt-bindings/clock/s3c2410.h>

​

#include "clk.h"

#include "clk-pll.h"

​

#define LOCKTIME    0x00

#define MPLLCON     0x04

#define UPLLCON     0x08

#define CLKCON      0x0c

#define CLKSLOW     0x10

#define CLKDIVN     0x14

#define CAMDIVN     0x18

​

/* the soc types */

enum supported_socs {

    S3C2410,

    S3C2440,

    S3C2442,

};

​

/* list of PLLs to be registered */

enum s3c2410_plls {

    mpll, upll,

};

​

static void __iomem *reg_base;

​

/*

 * list of controller registers to be saved and restored during a

 * suspend/resume cycle.

 */

static unsigned long s3c2410_clk_regs[] __initdata = {

    LOCKTIME,

    MPLLCON,

    UPLLCON,

    CLKCON,

    CLKSLOW,

    CLKDIVN,

    CAMDIVN,

};

​

PNAME(fclk_p) = { "mpll", "div_slow" };

​

static struct samsung_mux_clock s3c2410_common_muxes[] __initdata = {

    MUX(FCLK, "fclk", fclk_p, CLKSLOW, 4, 1),

};

​

static struct clk_div_table divslow_d[] = {

    { .val = 0, .div = 1 },

    { .val = 1, .div = 2 },

    { .val = 2, .div = 4 },

    { .val = 3, .div = 6 },

    { .val = 4, .div = 8 },

    { .val = 5, .div = 10 },

    { .val = 6, .div = 12 },

    { .val = 7, .div = 14 },

    { /* sentinel */ },

};

​

static struct samsung_div_clock s3c2410_common_dividers[] __initdata = {

    DIV_T(0, "div_slow", "xti", CLKSLOW, 0, 3, divslow_d),

    DIV(PCLK, "pclk", "hclk", CLKDIVN, 0, 1),

};

​

static struct samsung_gate_clock s3c2410_common_gates[] __initdata = {

    GATE(PCLK_SPI, "spi", "pclk", CLKCON, 18, 0, 0),

    GATE(PCLK_I2S, "i2s", "pclk", CLKCON, 17, 0, 0),

    GATE(PCLK_I2C, "i2c", "pclk", CLKCON, 16, 0, 0),

    GATE(PCLK_ADC, "adc", "pclk", CLKCON, 15, 0, 0),

    GATE(PCLK_RTC, "rtc", "pclk", CLKCON, 14, 0, 0),

    GATE(PCLK_GPIO, "gpio", "pclk", CLKCON, 13, CLK_IGNORE_UNUSED, 0),

    GATE(PCLK_UART2, "uart2", "pclk", CLKCON, 12, 0, 0),

    GATE(PCLK_UART1, "uart1", "pclk", CLKCON, 11, 0, 0),

    GATE(PCLK_UART0, "uart0", "pclk", CLKCON, 10, 0, 0),

    GATE(PCLK_SDI, "sdi", "pclk", CLKCON, 9, 0, 0),

    GATE(PCLK_PWM, "pwm", "pclk", CLKCON, 8, 0, 0),

    GATE(HCLK_USBD, "usb-device", "hclk", CLKCON, 7, 0, 0),

    GATE(HCLK_USBH, "usb-host", "hclk", CLKCON, 6, 0, 0),