linux-imx

/*

 *  Copyright 2011-2012 Calxeda, Inc.

 *  Copyright (C) 2012-2013 Altera Corporation <www.altera.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * Based from clk-highbank.c

 *

 */

#include <linux/slab.h>

#include <linux/clk-provider.h>

#include <linux/io.h>

#include <linux/mfd/syscon.h>

#include <linux/of.h>

#include <linux/regmap.h>

​

#include "clk.h"

​

#define SOCFPGA_L4_MP_CLK       "l4_mp_clk"

#define SOCFPGA_L4_SP_CLK       "l4_sp_clk"

#define SOCFPGA_NAND_CLK        "nand_clk"

#define SOCFPGA_NAND_X_CLK      "nand_x_clk"

#define SOCFPGA_MMC_CLK         "sdmmc_clk"

#define SOCFPGA_GPIO_DB_CLK_OFFSET  0xA8

​

#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)

​

/* SDMMC Group for System Manager defines */

#define SYSMGR_SDMMCGRP_CTRL_OFFSET    0x108

​

static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)

{

    u32 l4_src;

    u32 perpll_src;

​

    if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {

        l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);

        return l4_src &= 0x1;

    }

    if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {

        l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);

        return !!(l4_src & 2);

    }

​

    perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);

    if (streq(hwclk->init->name, SOCFPGA_MMC_CLK))

        return perpll_src &= 0x3;

    if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||

            streq(hwclk->init->name, SOCFPGA_NAND_X_CLK))

            return (perpll_src >> 2) & 3;

​

    /* QSPI clock */

    return (perpll_src >> 4) & 3;

​

}

​

static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent)

{

    u32 src_reg;

​

    if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {

        src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);

        src_reg &= ~0x1;

        src_reg |= parent;

        writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);

    } else if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {

        src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);

        src_reg &= ~0x2;

        src_reg |= (parent << 1);

        writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);

    } else {

        src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);

        if (streq(hwclk->init->name, SOCFPGA_MMC_CLK)) {

            src_reg &= ~0x3;

            src_reg |= parent;

        } else if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||

            streq(hwclk->init->name, SOCFPGA_NAND_X_CLK)) {

            src_reg &= ~0xC;

            src_reg |= (parent << 2);

        } else {/* QSPI clock */

            src_reg &= ~0x30;

            src_reg |= (parent << 4);

        }

        writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC);