linux-imx

/*

 *  Copyright 2011-2012 Calxeda, Inc.

 *  Copyright (C) 2012-2013 Altera Corporation <www.altera.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * Based from clk-highbank.c

 *

 */

#include <linux/slab.h>

#include <linux/clk-provider.h>

#include <linux/io.h>

#include <linux/of.h>

#include <linux/of_address.h>

​

#include "clk.h"

​

/* Clock bypass bits */

#define MAINPLL_BYPASS      (1<<0)

#define SDRAMPLL_BYPASS     (1<<1)

#define SDRAMPLL_SRC_BYPASS (1<<2)

#define PERPLL_BYPASS       (1<<3)

#define PERPLL_SRC_BYPASS   (1<<4)

​

#define SOCFPGA_PLL_BG_PWRDWN       0

#define SOCFPGA_PLL_EXT_ENA     1

#define SOCFPGA_PLL_PWR_DOWN        2

#define SOCFPGA_PLL_DIVF_MASK       0x0000FFF8

#define SOCFPGA_PLL_DIVF_SHIFT      3

#define SOCFPGA_PLL_DIVQ_MASK       0x003F0000

#define SOCFPGA_PLL_DIVQ_SHIFT      16

​

#define CLK_MGR_PLL_CLK_SRC_SHIFT   22

#define CLK_MGR_PLL_CLK_SRC_MASK    0x3

​

#define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw)

​

void __iomem *clk_mgr_base_addr;

​

static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,

                     unsigned long parent_rate)

{

    struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);

    unsigned long divf, divq, reg;

    unsigned long long vco_freq;

    unsigned long bypass;

​

    reg = readl(socfpgaclk->hw.reg);

    bypass = readl(clk_mgr_base_addr + CLKMGR_BYPASS);

    if (bypass & MAINPLL_BYPASS)

        return parent_rate;

​

    divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT;

    divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT;

    vco_freq = (unsigned long long)parent_rate * (divf + 1);