linux-imx

/*

 * SPEAr3xx machines clock framework source file

 *

 * Copyright (C) 2012 ST Microelectronics

 * Viresh Kumar <vireshk@kernel.org>

 *

 * This file is licensed under the terms of the GNU General Public

 * License version 2. This program is licensed "as is" without any

 * warranty of any kind, whether express or implied.

 */

​

#include <linux/clk.h>

#include <linux/clkdev.h>

#include <linux/err.h>

#include <linux/io.h>

#include <linux/of_platform.h>

#include <linux/spinlock_types.h>

#include "clk.h"

​

static DEFINE_SPINLOCK(_lock);

​

#define PLL1_CTR            (misc_base + 0x008)

#define PLL1_FRQ            (misc_base + 0x00C)

#define PLL2_CTR            (misc_base + 0x014)

#define PLL2_FRQ            (misc_base + 0x018)

#define PLL_CLK_CFG         (misc_base + 0x020)

    /* PLL_CLK_CFG register masks */

    #define MCTR_CLK_SHIFT      28

    #define MCTR_CLK_MASK       3

​

#define CORE_CLK_CFG            (misc_base + 0x024)

    /* CORE CLK CFG register masks */

    #define GEN_SYNTH2_3_CLK_SHIFT  18

    #define GEN_SYNTH2_3_CLK_MASK   1

​

    #define HCLK_RATIO_SHIFT    10

    #define HCLK_RATIO_MASK     2

    #define PCLK_RATIO_SHIFT    8

    #define PCLK_RATIO_MASK     2

​

#define PERIP_CLK_CFG           (misc_base + 0x028)

    /* PERIP_CLK_CFG register masks */

    #define UART_CLK_SHIFT      4

    #define UART_CLK_MASK       1

    #define FIRDA_CLK_SHIFT     5

    #define FIRDA_CLK_MASK      2

    #define GPT0_CLK_SHIFT      8

    #define GPT1_CLK_SHIFT      11

    #define GPT2_CLK_SHIFT      12

    #define GPT_CLK_MASK        1

​

#define PERIP1_CLK_ENB          (misc_base + 0x02C)

    /* PERIP1_CLK_ENB register masks */

    #define UART_CLK_ENB        3

    #define SSP_CLK_ENB     5

    #define I2C_CLK_ENB     7

    #define JPEG_CLK_ENB        8

    #define FIRDA_CLK_ENB       10

    #define GPT1_CLK_ENB        11

    #define GPT2_CLK_ENB        12

    #define ADC_CLK_ENB     15

    #define RTC_CLK_ENB     17

    #define GPIO_CLK_ENB        18

    #define DMA_CLK_ENB     19

    #define SMI_CLK_ENB     21

    #define GMAC_CLK_ENB        23

    #define USBD_CLK_ENB        24

    #define USBH_CLK_ENB        25

    #define C3_CLK_ENB      31

​

#define RAS_CLK_ENB         (misc_base + 0x034)

    #define RAS_AHB_CLK_ENB     0

    #define RAS_PLL1_CLK_ENB    1

    #define RAS_APB_CLK_ENB     2

    #define RAS_32K_CLK_ENB     3

    #define RAS_24M_CLK_ENB     4

    #define RAS_48M_CLK_ENB     5

    #define RAS_PLL2_CLK_ENB    7

    #define RAS_SYNT0_CLK_ENB   8

    #define RAS_SYNT1_CLK_ENB   9

    #define RAS_SYNT2_CLK_ENB   10

    #define RAS_SYNT3_CLK_ENB   11

​

#define PRSC0_CLK_CFG           (misc_base + 0x044)

#define PRSC1_CLK_CFG           (misc_base + 0x048)

#define PRSC2_CLK_CFG           (misc_base + 0x04C)

#define AMEM_CLK_CFG            (misc_base + 0x050)

    #define AMEM_CLK_ENB        0

​

#define CLCD_CLK_SYNT           (misc_base + 0x05C)

#define FIRDA_CLK_SYNT          (misc_base + 0x060)

#define UART_CLK_SYNT           (misc_base + 0x064)