linux-imx

/*

 * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>

 *

 * Based on ccu-sun8i-h3.c, which is:

 * Copyright (c) 2016 Maxime Ripard. All rights reserved.

 *

 * This software is licensed under the terms of the GNU General Public

 * License version 2, as published by the Free Software Foundation, and

 * may be copied, distributed, and modified under those terms.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

​

#include <linux/clk-provider.h>

#include <linux/of_address.h>

​

#include "ccu_common.h"

#include "ccu_reset.h"

​

#include "ccu_div.h"

#include "ccu_gate.h"

#include "ccu_mp.h"

#include "ccu_mult.h"

#include "ccu_nk.h"

#include "ccu_nkm.h"

#include "ccu_nkmp.h"

#include "ccu_nm.h"

#include "ccu_phase.h"

​

#include "ccu-sun8i-v3s.h"

​

static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",

                     "osc24M", 0x000,

                     8, 5,  /* N */

                     4, 2,  /* K */

                     0, 2,  /* M */

                     16, 2, /* P */

                     BIT(31),   /* gate */

                     BIT(28),   /* lock */

                     0);

​

/*

 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from

 * the base (2x, 4x and 8x), and one variable divider (the one true

 * pll audio).

 *

 * We don't have any need for the variable divider for now, so we just

 * hardcode it to match with the clock names

 */

#define SUN8I_V3S_PLL_AUDIO_REG 0x008

​

static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",

                   "osc24M", 0x008,

                   8, 7,    /* N */

                   0, 5,    /* M */

                   BIT(31), /* gate */

                   BIT(28), /* lock */

                   0);

​

static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",

                    "osc24M", 0x0010,

                    8, 7,       /* N */

                    0, 4,       /* M */

                    BIT(24),    /* frac enable */

                    BIT(25),    /* frac select */

                    270000000,  /* frac rate 0 */

                    297000000,  /* frac rate 1 */

                    BIT(31),    /* gate */

                    BIT(28),    /* lock */

                    0);

​

static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",

                    "osc24M", 0x0018,

                    8, 7,       /* N */

                    0, 4,       /* M */

                    BIT(24),    /* frac enable */

                    BIT(25),    /* frac select */

                    270000000,  /* frac rate 0 */

                    297000000,  /* frac rate 1 */

                    BIT(31),    /* gate */

                    BIT(28),    /* lock */

                    0);

​

static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",

                    "osc24M", 0x020,

                    8, 5,   /* N */

                    4, 2,   /* K */

                    0, 2,   /* M */

                    BIT(31),    /* gate */