linux-imx

/*

 * Zynq clock controller

 *

 *  Copyright (C) 2012 - 2013 Xilinx

 *

 *  Sören Brinkmann <soren.brinkmann@xilinx.com>

 *

 * This program is free software: you can redistribute it and/or modify

 * it under the terms of the GNU General Public License v2 as published by

 * the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

 */

​

#include <linux/clk/zynq.h>

#include <linux/clk.h>

#include <linux/clk-provider.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/slab.h>

#include <linux/string.h>

#include <linux/io.h>

​

static void __iomem *zynq_clkc_base;

​

#define SLCR_ARMPLL_CTRL        (zynq_clkc_base + 0x00)

#define SLCR_DDRPLL_CTRL        (zynq_clkc_base + 0x04)

#define SLCR_IOPLL_CTRL         (zynq_clkc_base + 0x08)

#define SLCR_PLL_STATUS         (zynq_clkc_base + 0x0c)

#define SLCR_ARM_CLK_CTRL       (zynq_clkc_base + 0x20)

#define SLCR_DDR_CLK_CTRL       (zynq_clkc_base + 0x24)

#define SLCR_DCI_CLK_CTRL       (zynq_clkc_base + 0x28)

#define SLCR_APER_CLK_CTRL      (zynq_clkc_base + 0x2c)

#define SLCR_GEM0_CLK_CTRL      (zynq_clkc_base + 0x40)

#define SLCR_GEM1_CLK_CTRL      (zynq_clkc_base + 0x44)

#define SLCR_SMC_CLK_CTRL       (zynq_clkc_base + 0x48)

#define SLCR_LQSPI_CLK_CTRL     (zynq_clkc_base + 0x4c)

#define SLCR_SDIO_CLK_CTRL      (zynq_clkc_base + 0x50)

#define SLCR_UART_CLK_CTRL      (zynq_clkc_base + 0x54)

#define SLCR_SPI_CLK_CTRL       (zynq_clkc_base + 0x58)

#define SLCR_CAN_CLK_CTRL       (zynq_clkc_base + 0x5c)

#define SLCR_CAN_MIOCLK_CTRL        (zynq_clkc_base + 0x60)

#define SLCR_DBG_CLK_CTRL       (zynq_clkc_base + 0x64)

#define SLCR_PCAP_CLK_CTRL      (zynq_clkc_base + 0x68)

#define SLCR_FPGA0_CLK_CTRL     (zynq_clkc_base + 0x70)

#define SLCR_621_TRUE           (zynq_clkc_base + 0xc4)

#define SLCR_SWDT_CLK_SEL       (zynq_clkc_base + 0x204)

​

#define NUM_MIO_PINS    54

​

#define DBG_CLK_CTRL_CLKACT_TRC     BIT(0)

#define DBG_CLK_CTRL_CPU_1XCLKACT   BIT(1)

​

enum zynq_clk {

    armpll, ddrpll, iopll,

    cpu_6or4x, cpu_3or2x, cpu_2x, cpu_1x,

    ddr2x, ddr3x, dci,

    lqspi, smc, pcap, gem0, gem1, fclk0, fclk1, fclk2, fclk3, can0, can1,

    sdio0, sdio1, uart0, uart1, spi0, spi1, dma,

    usb0_aper, usb1_aper, gem0_aper, gem1_aper,

    sdio0_aper, sdio1_aper, spi0_aper, spi1_aper, can0_aper, can1_aper,

    i2c0_aper, i2c1_aper, uart0_aper, uart1_aper, gpio_aper, lqspi_aper,

    smc_aper, swdt, dbg_trc, dbg_apb, clk_max};

​

static struct clk *ps_clk;

static struct clk *clks[clk_max];

static struct clk_onecell_data clk_data;

​

static DEFINE_SPINLOCK(armpll_lock);

static DEFINE_SPINLOCK(ddrpll_lock);

static DEFINE_SPINLOCK(iopll_lock);

static DEFINE_SPINLOCK(armclk_lock);

static DEFINE_SPINLOCK(swdtclk_lock);

static DEFINE_SPINLOCK(ddrclk_lock);

static DEFINE_SPINLOCK(dciclk_lock);

static DEFINE_SPINLOCK(gem0clk_lock);

static DEFINE_SPINLOCK(gem1clk_lock);

static DEFINE_SPINLOCK(canclk_lock);

static DEFINE_SPINLOCK(canmioclk_lock);

static DEFINE_SPINLOCK(dbgclk_lock);

static DEFINE_SPINLOCK(aperclk_lock);

​

static const char *const armpll_parents[] __initconst = {"armpll_int",

    "ps_clk"};

static const char *const ddrpll_parents[] __initconst = {"ddrpll_int",

    "ps_clk"};