linux-imx

/*

 * Zynq PLL driver

 *

 *  Copyright (C) 2013 Xilinx

 *

 *  Sören Brinkmann <soren.brinkmann@xilinx.com>

 *

 * This program is free software: you can redistribute it and/or modify

 * it under the terms of the GNU General Public License v2 as published by

 * the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

 *

 */

#include <linux/clk/zynq.h>

#include <linux/clk-provider.h>

#include <linux/slab.h>

#include <linux/io.h>

​

/**

 * struct zynq_pll

 * @hw:     Handle between common and hardware-specific interfaces

 * @pll_ctrl:   PLL control register

 * @pll_status: PLL status register

 * @lock:   Register lock

 * @lockbit:    Indicates the associated PLL_LOCKED bit in the PLL status

 *      register.

 */

struct zynq_pll {

    struct clk_hw   hw;

    void __iomem    *pll_ctrl;

    void __iomem    *pll_status;

    spinlock_t  *lock;

    u8      lockbit;

};

#define to_zynq_pll(_hw)    container_of(_hw, struct zynq_pll, hw)

​

/* Register bitfield defines */

#define PLLCTRL_FBDIV_MASK  0x7f000

#define PLLCTRL_FBDIV_SHIFT 12

#define PLLCTRL_BPQUAL_MASK (1 << 3)

#define PLLCTRL_PWRDWN_MASK 2

#define PLLCTRL_PWRDWN_SHIFT    1

#define PLLCTRL_RESET_MASK  1

#define PLLCTRL_RESET_SHIFT 0

​

#define PLL_FBDIV_MIN   13

#define PLL_FBDIV_MAX   66

​

/**

 * zynq_pll_round_rate() - Round a clock frequency

 * @hw:     Handle between common and hardware-specific interfaces

 * @rate:   Desired clock frequency

 * @prate:  Clock frequency of parent clock

 * Returns frequency closest to @rate the hardware can generate.

 */

static long zynq_pll_round_rate(struct clk_hw *hw, unsigned long rate,

        unsigned long *prate)

{

    u32 fbdiv;

​

    fbdiv = DIV_ROUND_CLOSEST(rate, *prate);

    if (fbdiv < PLL_FBDIV_MIN)

        fbdiv = PLL_FBDIV_MIN;

    else if (fbdiv > PLL_FBDIV_MAX)

        fbdiv = PLL_FBDIV_MAX;

​

    return *prate * fbdiv;

}

​

/**

 * zynq_pll_recalc_rate() - Recalculate clock frequency

 * @hw:         Handle between common and hardware-specific interfaces

 * @parent_rate:    Clock frequency of parent clock

 * Returns current clock frequency.

 */

static unsigned long zynq_pll_recalc_rate(struct clk_hw *hw,

        unsigned long parent_rate)

{

    struct zynq_pll *clk = to_zynq_pll(hw);

    u32 fbdiv;

​

    /*

     * makes probably sense to redundantly save fbdiv in the struct

     * zynq_pll to save the IO access.

     */