Source
/*
* Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com)
* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1, Each can be
* programmed to go from @count to @limit and optionally interrupt.
* We've designated TIMER0 for clockevents and TIMER1 for clocksource
*
* ARCv2 based HS38 cores have RTC (in-core) and GFRC (inside ARConnect/MCIP)
* which are suitable for UP and SMP based clocksources respectively
*/
static unsigned long arc_timer_freq;
static int noinline arc_get_timer_clk(struct device_node *node)
{
struct clk *clk;
int ret;
clk = of_clk_get(node, 0);
if (IS_ERR(clk)) {
pr_err("timer missing clk\n");
return PTR_ERR(clk);
}
ret = clk_prepare_enable(clk);
if (ret) {
pr_err("Couldn't enable parent clk\n");
return ret;
}
arc_timer_freq = clk_get_rate(clk);
return 0;
}
/********** Clock Source Device *********/
static u64 arc_read_gfrc(struct clocksource *cs)
{
unsigned long flags;
u32 l, h;