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/*
* J-Core SoC PIT/clocksource driver
*
* Copyright (C) 2015-2016 Smart Energy Instruments, Inc.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
struct jcore_pit {
struct clock_event_device ced;
void __iomem *base;
unsigned long periodic_delta;
u32 enable_val;
};
static void __iomem *jcore_pit_base;
static struct jcore_pit __percpu *jcore_pit_percpu;
static notrace u64 jcore_sched_clock_read(void)
{
u32 seclo, nsec, seclo0;
__iomem void *base = jcore_pit_base;
seclo = readl(base + REG_SECLO);
do {
seclo0 = seclo;
nsec = readl(base + REG_NSEC);
seclo = readl(base + REG_SECLO);
} while (seclo0 != seclo);
return seclo * NSEC_PER_SEC + nsec;
}
static u64 jcore_clocksource_read(struct clocksource *cs)
{
return jcore_sched_clock_read();
}
static int jcore_pit_disable(struct jcore_pit *pit)
{
writel(0, pit->base + REG_PITEN);
return 0;
}
static int jcore_pit_set(unsigned long delta, struct jcore_pit *pit)
{
jcore_pit_disable(pit);
writel(delta, pit->base + REG_THROT);
writel(pit->enable_val, pit->base + REG_PITEN);
return 0;
}
static int jcore_pit_set_state_shutdown(struct clock_event_device *ced)
{
struct jcore_pit *pit = container_of(ced, struct jcore_pit, ced);
return jcore_pit_disable(pit);
}
static int jcore_pit_set_state_oneshot(struct clock_event_device *ced)
{
struct jcore_pit *pit = container_of(ced, struct jcore_pit, ced);
return jcore_pit_disable(pit);
}