linux-imx

// SPDX-License-Identifier: GPL-2.0

/*

 * SuperH Timer Support - CMT

 *

 *  Copyright (C) 2008 Magnus Damm

 */

​

#include <linux/clk.h>

#include <linux/clockchips.h>

#include <linux/clocksource.h>

#include <linux/delay.h>

#include <linux/err.h>

#include <linux/init.h>

#include <linux/interrupt.h>

#include <linux/io.h>

#include <linux/ioport.h>

#include <linux/irq.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/of_device.h>

#include <linux/platform_device.h>

#include <linux/pm_domain.h>

#include <linux/pm_runtime.h>

#include <linux/sh_timer.h>

#include <linux/slab.h>

#include <linux/spinlock.h>

​

struct sh_cmt_device;

​

/*

 * The CMT comes in 5 different identified flavours, depending not only on the

 * SoC but also on the particular instance. The following table lists the main

 * characteristics of those flavours.

 *

 *          16B 32B 32B-F   48B R-Car Gen2

 * -----------------------------------------------------------------------------

 * Channels     2   1/4 1   6   2/8

 * Control Width    16  16  16  16  32

 * Counter Width    16  32  32  32/48   32/48

 * Shared Start/Stop    Y   Y   Y   Y   N

 *

 * The r8a73a4 / R-Car Gen2 version has a per-channel start/stop register

 * located in the channel registers block. All other versions have a shared

 * start/stop register located in the global space.

 *

 * Channels are indexed from 0 to N-1 in the documentation. The channel index

 * infers the start/stop bit position in the control register and the channel

 * registers block address. Some CMT instances have a subset of channels

 * available, in which case the index in the documentation doesn't match the

 * "real" index as implemented in hardware. This is for instance the case with

 * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0

 * in the documentation but using start/stop bit 5 and having its registers

 * block at 0x60.

 *

 * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit

 * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable.

 */

​

enum sh_cmt_model {

    SH_CMT_16BIT,

    SH_CMT_32BIT,

    SH_CMT_48BIT,

    SH_CMT0_RCAR_GEN2,

    SH_CMT1_RCAR_GEN2,

};

​

struct sh_cmt_info {

    enum sh_cmt_model model;

​

    unsigned int channels_mask;

​

    unsigned long width; /* 16 or 32 bit version of hardware block */

    u32 overflow_bit;

    u32 clear_bits;

​

    /* callbacks for CMSTR and CMCSR access */

    u32 (*read_control)(void __iomem *base, unsigned long offs);

    void (*write_control)(void __iomem *base, unsigned long offs,

                  u32 value);

​

    /* callbacks for CMCNT and CMCOR access */

    u32 (*read_count)(void __iomem *base, unsigned long offs);

    void (*write_count)(void __iomem *base, unsigned long offs, u32 value);

};

​

struct sh_cmt_channel {

    struct sh_cmt_device *cmt;

​

    unsigned int index; /* Index in the documentation */

    unsigned int hwidx; /* Real hardware index */

​

    void __iomem *iostart;