linux-imx

// SPDX-License-Identifier: GPL-2.0

/*

 * SuperH Timer Support - MTU2

 *

 *  Copyright (C) 2009 Magnus Damm

 */

​

#include <linux/clk.h>

#include <linux/clockchips.h>

#include <linux/delay.h>

#include <linux/err.h>

#include <linux/init.h>

#include <linux/interrupt.h>

#include <linux/io.h>

#include <linux/ioport.h>

#include <linux/irq.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/platform_device.h>

#include <linux/pm_domain.h>

#include <linux/pm_runtime.h>

#include <linux/sh_timer.h>

#include <linux/slab.h>

#include <linux/spinlock.h>

​

struct sh_mtu2_device;

​

struct sh_mtu2_channel {

    struct sh_mtu2_device *mtu;

    unsigned int index;

​

    void __iomem *base;

​

    struct clock_event_device ced;

};

​

struct sh_mtu2_device {

    struct platform_device *pdev;

​

    void __iomem *mapbase;

    struct clk *clk;

​

    raw_spinlock_t lock; /* Protect the shared registers */

​

    struct sh_mtu2_channel *channels;

    unsigned int num_channels;

​

    bool has_clockevent;

};

​

#define TSTR -1 /* shared register */

#define TCR  0 /* channel register */

#define TMDR 1 /* channel register */

#define TIOR 2 /* channel register */

#define TIER 3 /* channel register */

#define TSR  4 /* channel register */

#define TCNT 5 /* channel register */

#define TGR  6 /* channel register */

​

#define TCR_CCLR_NONE       (0 << 5)

#define TCR_CCLR_TGRA       (1 << 5)

#define TCR_CCLR_TGRB       (2 << 5)

#define TCR_CCLR_SYNC       (3 << 5)

#define TCR_CCLR_TGRC       (5 << 5)

#define TCR_CCLR_TGRD       (6 << 5)

#define TCR_CCLR_MASK       (7 << 5)

#define TCR_CKEG_RISING     (0 << 3)

#define TCR_CKEG_FALLING    (1 << 3)

#define TCR_CKEG_BOTH       (2 << 3)

#define TCR_CKEG_MASK       (3 << 3)

/* Values 4 to 7 are channel-dependent */

#define TCR_TPSC_P1     (0 << 0)

#define TCR_TPSC_P4     (1 << 0)

#define TCR_TPSC_P16        (2 << 0)

#define TCR_TPSC_P64        (3 << 0)

#define TCR_TPSC_CH0_TCLKA  (4 << 0)

#define TCR_TPSC_CH0_TCLKB  (5 << 0)

#define TCR_TPSC_CH0_TCLKC  (6 << 0)

#define TCR_TPSC_CH0_TCLKD  (7 << 0)

#define TCR_TPSC_CH1_TCLKA  (4 << 0)

#define TCR_TPSC_CH1_TCLKB  (5 << 0)

#define TCR_TPSC_CH1_P256   (6 << 0)

#define TCR_TPSC_CH1_TCNT2  (7 << 0)

#define TCR_TPSC_CH2_TCLKA  (4 << 0)

#define TCR_TPSC_CH2_TCLKB  (5 << 0)

#define TCR_TPSC_CH2_TCLKC  (6 << 0)

#define TCR_TPSC_CH2_P1024  (7 << 0)

#define TCR_TPSC_CH34_P256  (4 << 0)

#define TCR_TPSC_CH34_P1024 (5 << 0)

#define TCR_TPSC_CH34_TCLKA (6 << 0)

#define TCR_TPSC_CH34_TCLKB (7 << 0)

#define TCR_TPSC_MASK       (7 << 0)